Patents by Inventor Jitendra Dasani

Jitendra Dasani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10878892
    Abstract: Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 29, 2020
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Shri Sagar Dwivedi, Fakhruddin Ali Bohra
  • Patent number: 10848186
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include first decoding circuitry that receives an address and partially decodes the address to generate a partially decoded address. The integrated circuit may include second decoding circuitry that receives the partially decoded address, generates a decoded address, and provides the decoded address to a wordline. The integrated circuit may include encoding circuitry that receives the decoded address from the wordline and encodes the decoded address to generate an encoded address. The integrated circuit may include comparing circuitry that receives the encoded address and compares the encoded address with the address to detect faults in the memory circuitry.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 24, 2020
    Assignee: Arm Limited
    Inventors: Vivek Asthana, Jitendra Dasani, Amit Chhabra
  • Patent number: 10839861
    Abstract: Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: November 17, 2020
    Assignee: Arm Limited
    Inventors: Vivek Nautiyal, Satinderjit Singh, Abhishek B. Akkur, Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Jungtae Kwon, Jitendra Dasani, Manoj Puthan Purayil
  • Patent number: 10748583
    Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 18, 2020
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Fakhruddin Ali Bohra, Shri Sagar Dwivedi
  • Patent number: 10734065
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include read circuitry coupled to bitlines, and the read circuitry may be activated based on a read select signal to perform a read operation on the bitlines. The integrated circuit may include write circuitry coupled to the bitlines, and the write circuitry may be activated based on a write select signal to perform a write operation on the bitlines. The integrated circuit may include bitline discharge control circuitry coupled to the bitlines and the write circuitry, and the bitline discharge control circuitry may control the bitline discharge of the bitlines during the read operation so as to restrict a false read on the bitlines by providing a discharge boundary for the bitlines during the read operation.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: August 4, 2020
    Assignee: Arm Limited
    Inventors: Rajiv Kumar Sisodia, Navin Agarwal, Shri Sagar Dwivedi, Jitendra Dasani, Fakhruddin Ali Bohra, Lalit Gupta, Daksheshkumar Maganbhai Malaviya
  • Patent number: 10672459
    Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: June 2, 2020
    Assignee: Arm Limited
    Inventors: Yicong Li, Andy Wangkun Chen, Sharryl Renee Dettmer, Lalit Gupta, Jitendra Dasani, Yeon Jun Park, Shri Sagar Dwivedi, Fakhruddin Ali Bohra
  • Patent number: 10622038
    Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 14, 2020
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Fakhruddin Ali Bohra, Jitendra Dasani, Shri Sagar Dwivedi, Vivek Nautiyal, Gaurav Rattan Singla
  • Publication number: 20200005836
    Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Lalit Gupta, Fakhruddin Ali Bohra, Jitendra Dasani, Shri Sagar Dwivedi, Vivek Nautiyal, Gaurav Rattan Singla
  • Publication number: 20190325949
    Abstract: Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Shri Sagar Dwivedi, Fakhruddin Ali Bohra
  • Patent number: 10425076
    Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: September 24, 2019
    Assignee: ARM Limited
    Inventors: Lalit Gupta, Vivek Nautiyal, Andy Wangkun Chen, Jitendra Dasani, Bo Zheng, Akshay Kumar, Vivek Asthana
  • Publication number: 20190253084
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include first decoding circuitry that receives an address and partially decodes the address to generate a partially decoded address. The integrated circuit may include second decoding circuitry that receives the partially decoded address, generates a decoded address, and provides the decoded address to a wordline. The integrated circuit may include encoding circuitry that receives the decoded address from the wordline and encodes the decoded address to generate an encoded address. The integrated circuit may include comparing circuitry that receives the encoded address and compares the encoded address with the address to detect faults in the memory circuitry.
    Type: Application
    Filed: February 13, 2018
    Publication date: August 15, 2019
    Inventors: Vivek Asthana, Jitendra Dasani, Amit Chhabra
  • Publication number: 20190244656
    Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.
    Type: Application
    Filed: February 7, 2018
    Publication date: August 8, 2019
    Inventors: Yicong Li, Andy Wangkun Chen, Sharryl Renee Dettmer, Lalit Gupta, Jitendra Dasani, Yeon Jun Park, Shri Sagar Dwivedi, Fakhruddin Ali Bohra
  • Publication number: 20190237135
    Abstract: Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.
    Type: Application
    Filed: February 1, 2018
    Publication date: August 1, 2019
    Inventors: Arjunesh Namboothiri Madhavan, Akash Bangalore Srinivasa, Sujit Kumar Rout, Vikash, Gaurav Rattan Singla, Vivek Nautiyal, Shri Sagar Dwivedi, Jitendra Dasani, Lalit Gupta
  • Publication number: 20190237111
    Abstract: Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.
    Type: Application
    Filed: January 26, 2018
    Publication date: August 1, 2019
    Inventors: Vivek Nautiyal, Satinderjit Singh, Abhishek B. Akkur, Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Jungtae Kwon, Jitendra Dasani, Manoj Puthan Purayil
  • Publication number: 20190198064
    Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Fakhruddin Ali Bohra, Shri Sagar Dwivedi
  • Publication number: 20190122724
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to multiple dummy wordline loads via a dummy wordline. The integrated circuit may include demultiplexer circuitry coupled to a first path of the dummy wordline between the dummy wordline driver and the multiple dummy wordline loads. The integrated circuit may include multiplexer circuitry coupled to a second path of the dummy wordline between the multiple dummy wordline loads and a dummy bitline load. The demultiplexer circuitry and the multiplexer circuitry may be controlled with one or more selection signals to select at least one of the multiple dummy wordline loads.
    Type: Application
    Filed: October 20, 2017
    Publication date: April 25, 2019
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Fakhruddin Ali Bohra
  • Patent number: 10269416
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to multiple dummy wordline loads via a dummy wordline. The integrated circuit may include demultiplexer circuitry coupled to a first path of the dummy wordline between the dummy wordline driver and the multiple dummy wordline loads. The integrated circuit may include multiplexer circuitry coupled to a second path of the dummy wordline between the multiple dummy wordline loads and a dummy bitline load. The demultiplexer circuitry and the multiplexer circuitry may be controlled with one or more selection signals to select at least one of the multiple dummy wordline loads.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: April 23, 2019
    Assignee: ARM Limited
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Fakhruddin Ali Bohra
  • Publication number: 20190066770
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include read circuitry coupled to bitlines, and the read circuitry may be activated based on a read select signal to perform a read operation on the bitlines. The integrated circuit may include write circuitry coupled to the bitlines, and the write circuitry may be activated based on a write select signal to perform a write operation on the bitlines. The integrated circuit may include bitline discharge control circuitry coupled to the bitlines and the write circuitry, and the bitline discharge control circuitry may control the bitline discharge of the bitlines during the read operation so as to restrict a false read on the bitlines by providing a discharge boundary for the bitlines during the read operation.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 28, 2019
    Inventors: Rajiv Kumar Sisodia, Navin Agarwal, Shri Sagar Dwivedi, Jitendra Dasani, Fakhruddin Ali Bohra, Lalit Gupta, Daksheshkumar Maganbhai Malaviya
  • Patent number: 10217496
    Abstract: Various implementations described herein are directed to an integrated circuit with memory circuitry having an array of bitcells that are accessible via multiple bitlines. The integrated circuit may include a write driver coupled to at least one bitline of the multiple bitlines through a column multiplexer. The integrated circuit may include a pass transistor coupled to the write driver and the column multiplexer via a write data line. The integrated circuit may include a charge storage device coupled between the pass transistor and write assist enable circuitry. The integrated circuit may include a transmission gate coupled to a gate of the write driver. The integrated circuit may include a clamp transistor coupled between the gate of write driver and the charge storage device such that the clamp transistor receives a voltage assist signal from the charge storage device at the gate of the write driver.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: February 26, 2019
    Assignee: ARM Limited
    Inventors: Vivek Nautiyal, Jitendra Dasani, Satinderjit Singh, Shri Sagar Dwivedi, Bo Zheng, Fakhruddin Ali Bohra
  • Publication number: 20190057735
    Abstract: A circuit includes a dummy wordline, a dummy bitline, and a dummy cell coupled to the dummy bitline. The dummy cell includes an active pulldown nMOSFET and a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and a drain terminal connected to the dummy bitline. The circuit further includes a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to a substrate.
    Type: Application
    Filed: August 17, 2017
    Publication date: February 21, 2019
    Inventors: Abhishek B. Akkur, Jitendra Dasani, Shri Sagar Dwivedi, Vivek Nautiyal, Satinderjit Singh, Vasimraja Bhavikatti