Abstract: An autonomous cleaning system bridge includes a pair of parallel beams and a pair of transverse beam assemblies interposed between the pair of parallel beams and disposed in spaced relation to one another. Each transverse beam assembly includes an outer tube extending between a first end portion coupled to a first parallel beam and an opposite, second end portion, an insert coupled to the second end portion and defining a through-bore, and an inner tube extending between a first end portion and an opposite, second end portion, the second end portion of the inner tube coupled to a second parallel beam, wherein the inner tube is slidably supported within the through-bore to enable to autonomous cleaning system bridge to transition from a first, expanded configuration to a second, collapsed configuration due to contact between the second parallel beam and a portion of a solar tracker system.

Abstract: A solar tracker system including at least two solar trackers arranged substantially in parallel, each solar tracker including a torque tube and a plurality of piers supporting the torque tube, a drive mechanism mounted on one of the plurality of piers associated with a first of the at least two solar trackers to rotate the first of the at least two solar trackers, a pulley mounted on each torque tube of the at least two solar trackers, and a cable connecting the pulley of the first of the at least two solar trackers to the pulley of a second of the at least two solar trackers, wherein rotation of the first of the at least two solar trackers is translated to the second of the at least two solar trackers via the cable.

Abstract: Disclosed herein are methods, systems, and processes to provide coherency across disjoint caches in clustered environments. It is determined whether a data object is owned by an owner node, where the owner node is one of multiple nodes of a cluster. If the owner node for the data object is identified by the determining, a request is sent to the owner node for the data object. However, if the owner node for the data object is not identified by the determining, selects a node in the cluster is selected as the owner node, and the request for the data object is sent to the owner node.

Abstract: An information handling system may include a processor, a data processing unit communicatively coupled to the processor, and a management controller communicatively coupled to the processor and the data processing unit and configured for out-of-band management of the information handling system. The management controller may further be configured to obtain a hardware inventory and capabilities of the data processing unit; based on the hardware inventory and capabilities, generate a firmware capsule for execution during a basic input/output system phase of the data processing unit to cause a secure erasure of contents of a memory of the data processing unit; and communicate the firmware capsule to the data processing unit during an operating system phase of the data processing unit and cause the data processing unit to reboot to its basic input/output system phase in order to execute drivers of the firmware capsule in order to securely erase the memory.

Abstract: The present disclosure encompasses solid state forms of Vericiguat, in embodiments crystalline polymorphs of Vericiguat, processes for preparation thereof, and pharmaceutical compositions thereof.

Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

Abstract: Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.

Abstract: Systems and methods are provided for planning a future network topology with associated configuration settings of existing nodes in a network and enacting changes to the configuration settings after the network has been physically changed to the planned future topology. The method can include, in response to receiving a topology plan to change a network from an initial network topology to a future network topology, determine a configuration plan to change configuration settings of one or more existing Network Elements (NEs) deployed in the network in order to transition the network from the initial network topology to the future network topology, and, in response to discovering that the network has been physically changed to match the future network topology, automatically enact the configuration plan to change the configuration settings of the one or more existing NEs.

Abstract: Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.

Abstract: This document discloses a solution for managing multiple subscriber identifiers in a network node. According to an aspect, a method for a first network node comprises: storing at least two subscriber identifiers; triggering a handover procedure for a first subscriber identifier of the at least two subscriber identifiers; and transmitting, during the handover procedure, a handover message to a second network node, the second network node managing a target cell for the handover procedure, wherein the handover message comprises at least a second subscriber identifier of the at least two subscriber identifiers.

Abstract: A method for processing data, comprising receiving a folder attached request at a virtual media service operating on a processor, creating a virtual image data file and lookup table in response to the folder attached request at the virtual media service, preparing content to be populated into a master boot record region in response to the folder attached request and generating a virtual USB device in response to the populated master boot record.

Abstract: A method for processing data, comprising receiving a folder attached request at a virtual media service operating on a processor, creating a virtual image data file and lookup table in response to the folder attached request at the virtual media service, preparing content to be populated into a master boot record region in response to the folder attached request and generating a virtual USB device in response to the populated master boot record.

Abstract: Disclosed herein are integrated circuit (IC) devices with contacts using nitridized molybdenum. For example, a contact arrangement for an IC device may include a semiconductor material and a contact extending into a portion of the semiconductor material. The contact may include molybdenum. The molybdenum may be in a first layer and a second layer, where the second layer may further include nitrogen. The first layer may have a thickness between about 5 nanometers and 16 nanometers, and the second layer may have a thickness between about 0.5 nanometers to 2.5 nanometers. The contact may further include a fill material (e.g., an electrically conductive material) and the second layer may be in contact with the fill material. The molybdenum may have a low resistance, and thus may improve the electrical performance of the contact. The nitridized molybdenum may prevent oxidation during the fabrication of the contact.

Abstract: An EB-PVD technique was used to fabricate ceramic/polymer/ceramic (LAGP/PE/LAGP) hybrid separator for rechargeable LIBs and Li batteries. The application of a ceramic electrolyte (LAGP) layer on traditional PE separator soaked in 1-M LiAsF6 liquid electrolyte combined the best attributes of traditional PE separator and solid inorganic electrolytes. The synergistic behavior of hybrid separator resulted in a high mechanical stability/flexibility, increased liquid uptake, high ion conduction, reduced cell voltage polarization, no lithium dendrite formation, and increased usable lithium content as compared to the state-of-the-art PE separator used in LIBs. The functional separator can be used to prolong life cycle and power capability of present LIBs. Thickness and density optimization of LAGP or similar electrolytes on polymer or other battery separators and their use in full Li battery (LIB, Li—S, Li—O2, Li-Ph, flow battery) cells are expected to further improve performance.

Abstract: A throttle control and safety switch device that serves the dual function of adjusting a throttle of an ATV (all-terrain vehicle) while turning off the engine in the event of failure of a throttle cable or if the throttle cable is stuck, is disclosed. The throttle control and safety switch device includes an operating lever connected to a pivot shaft for pivotal movement about an axis (A-A?). A first carrier connected to the pivot shaft includes a safety switch and a cable attachment portion to engage a throttle actuating cable. The safety switch transmits a cutoff signal to an electronic control unit (ECU) upon actuation by a plunger portion of a second carrier pivotally connected to the pivot shaft via fastener and connected to the first carrier via a dowel and slot arrangement.

Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

Abstract: A method is provided for performing power validation on an integrated circuit (IC) design based on a power assertion specification. The method includes receiving the power assertion specification for the IC design, where the power assertion specification includes a predicted power consumption. Power consumption of the IC design is estimated according to power assertions specified in the power assertion specification. The estimated power consumption is compared against the predicted power consumption included in the power assertion specification. The IC design is determined to be associated with a power assertion failure based on results of the comparing. In response to determining that the IC design is associated with the power assertion failure, the IC design is refined to remedy the power assertion failure.

Abstract: Disclosed are apparatuses, systems, and techniques that improve memory and computational efficiency of remote direct memory accesses into a memory of a graphics processing unit. The techniques include but are not limited to receiving packets with video frame data, storing the plurality of packets in a memory of a network controller, processing the packets to obtain unit(s) of the video frame, storing the unit(s) representative of the video frame in a memory of a graphics processing unit (GPU), and extracting the data of the video frame from the units representative of the video frame, stored in the memory of the GPU, to render the video frame.

Abstract: Various systems and methods are described for deployment, import, and scheduling of containers and other software components on cloud and edge computing hardware. A development platform may receive, from a remote location, package data for a deployment of one or more containers, including a configuration for the one or more containers. Such package data may be provided by a Helm chart or a Docker Compose YAML file. The development platform may extract the configuration for the one or more containers from the package data, and also perform a security evaluation of the one or more containers and the configuration for the one or more containers to validate compliance with a security policy. The development platform may execute (and coordinate scheduling) of one or more container images for the one or more containers, based on the configuration, after validating compliance with the security policy.

Abstract: The present disclosure relates to dynamically updating a delay line code. A method for updating the delay line code may include receiving a strobe input at a coarse delay line. The method may further include receiving a coarse delay cell code at the coarse delay line. The method may also include generating a first clock path based upon a first chain of interleaved logic gates included within the coarse delay line. The method may additionally include generating a second clock path based upon a second chain of interleaved logic gates included within the coarse delay line. The method may further include receiving the first clock path, and the second clock path, and a fine delay cell code at a fine delay cell. The method may also include generating a strobe delayed output based upon the first clock path, and the second clock path, and the fine delay code.