Abstract: A throttle control and safety switch device that serves the dual function of adjusting a throttle of an ATV (all-terrain vehicle) while turning off the engine in the event of failure of a throttle cable or if the throttle cable is stuck, is disclosed. The throttle control and safety switch device includes an operating lever connected to a pivot shaft for pivotal movement about an axis (A-A?). A first carrier connected to the pivot shaft includes a safety switch and a cable attachment portion to engage a throttle actuating cable. The safety switch transmits a cutoff signal to an electronic control unit (ECU) upon actuation by a plunger portion of a second carrier pivotally connected to the pivot shaft via fastener and connected to the first carrier via a dowel and slot arrangement.

Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

Abstract: A method is provided for performing power validation on an integrated circuit (IC) design based on a power assertion specification. The method includes receiving the power assertion specification for the IC design, where the power assertion specification includes a predicted power consumption. Power consumption of the IC design is estimated according to power assertions specified in the power assertion specification. The estimated power consumption is compared against the predicted power consumption included in the power assertion specification. The IC design is determined to be associated with a power assertion failure based on results of the comparing. In response to determining that the IC design is associated with the power assertion failure, the IC design is refined to remedy the power assertion failure.

Abstract: Various systems and methods are described for deployment, import, and scheduling of containers and other software components on cloud and edge computing hardware. A development platform may receive, from a remote location, package data for a deployment of one or more containers, including a configuration for the one or more containers. Such package data may be provided by a Helm chart or a Docker Compose YAML file. The development platform may extract the configuration for the one or more containers from the package data, and also perform a security evaluation of the one or more containers and the configuration for the one or more containers to validate compliance with a security policy. The development platform may execute (and coordinate scheduling) of one or more container images for the one or more containers, based on the configuration, after validating compliance with the security policy.

Abstract: Disclosed are apparatuses, systems, and techniques that improve memory and computational efficiency of remote direct memory accesses into a memory of a graphics processing unit. The techniques include but are not limited to receiving packets with video frame data, storing the plurality of packets in a memory of a network controller, processing the packets to obtain unit(s) of the video frame, storing the unit(s) representative of the video frame in a memory of a graphics processing unit (GPU), and extracting the data of the video frame from the units representative of the video frame, stored in the memory of the GPU, to render the video frame.

Abstract: The present disclosure relates to dynamically updating a delay line code. A method for updating the delay line code may include receiving a strobe input at a coarse delay line. The method may further include receiving a coarse delay cell code at the coarse delay line. The method may also include generating a first clock path based upon a first chain of interleaved logic gates included within the coarse delay line. The method may additionally include generating a second clock path based upon a second chain of interleaved logic gates included within the coarse delay line. The method may further include receiving the first clock path, and the second clock path, and a fine delay cell code at a fine delay cell. The method may also include generating a strobe delayed output based upon the first clock path, and the second clock path, and the fine delay code.

Abstract: In one embodiment, layers comprising Carbon (e.g., Silicon Carbide) are on source/drain regions of a transistor, e.g., before gate formation and metallization, and the layers comprising Carbon are later removed in the manufacturing process to form electrical contacts on the source/drain regions.

Abstract: Semiconductor structures having a source and/or drain with a refractory metal cap, and methods of forming the same, are described herein. In one example, a semiconductor structure includes a channel, a gate, a source, and a drain. The source and drain contain silicon and germanium, and one or both of the source and drain are capped with a semiconductor cap and a refractory metal cap. The semiconductor cap is on the source and/or drain and contains germanium and boron. The refractory metal cap is on the semiconductor cap and contains a refractory metal.

Abstract: Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.

Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.

Abstract: An Information Handling System (IHS) includes multiple hardware devices, and a Baseboard Management Controller (BMC) in communication with the hardware devices. The BMC includes executable code to cause the BMC to receive a message associated with a non-registered hardware device that is not registered to be managed by the BMC in which the message formatted according to a native protocol of the BMC. The code further causes the code to transmit the message to a device plugin associated with the non-registered hardware device in which the device plugin comprises custom instructions that, upon execution by a system processor, cause the IHS to convert the message into a protocol associated with the non-registered hardware device, and forward the converted message to the non-registered hardware device using the protocol of the non-registered hardware device.

Abstract: A system includes a computing device that includes a memory configured to store instructions. The computing device also includes a processor to execute the instructions to perform operations that include receiving data representing one or more user-selected item attributes. The data includes one of at least four selectable interest levels for each of the one or more user-selected item attributes. Operations also include identifying one or more items representative of the selected interest level for each of the one or more user-selected item attributes, and initiating delivery of data representing the identified one or more items for user selection.

Abstract: An oropharyngeal dam for facilitating a safe and efficient dental treatment is disclosed. The oropharyngeal dam includes a pair of cheek retractors including an upper retractor component, a lower retractor component and a cheek retracting sheet. Further, the upper retractor component, the lower retractor component, the cheek retracting sheet, and a set of lip retractors are collectively configured to retract cheeks of a patient. The oropharyngeal dam includes a tongue protector including an upper protector component, a lower protector component and a tongue protecting sheet. Furthermore, the upper protector component, the lower protector component and the tongue protecting sheet are collectively configured to shield and retract a tongue of the patient. The set of lip retractors are configured to aid lip retraction when pulled outside the mouth.

Abstract: A system and method for converting raw frame data to a video file. Instead of converting all raw frame raw for each frame, embodiments create a mapping table and compare a mapping of the raw frame data for a current frame with a mapping of the raw frame data for a previous frame to determine if raw frame data changed from a previous frame to the current frame. Embodiments convert only the new raw frame data and update the mapping table with the new raw frame data, whereby the processing resources and time needed to convert raw frame data into a video file may be greatly reduced.

Abstract: An information handling system may include a management controller configured to provide out-of-band management of the information handling system. The information handling system may further include a network interface controller. The management controller may be configured to: receive management data from the network interface controller; and redirect the management data to a remote console.

Abstract: An information handling system may include a host system that includes a host system processor and a host system memory coupled to the host system processor. The information handling system may further include a management controller configured to provide out-of-band management of the host system. The management controller may be configured to establish a virtual console session between the host system and a remote terminal. The management controller may further be configured to, in response to a command from the remote terminal to send data from the remote terminal to the host system, receive the data from the remote terminal; and transmit the data to the host system character-by-character via a keyboard interface of the host system.

Abstract: An information handling system may include a processor, a data processing unit communicatively coupled to the processor, and a management controller communicatively coupled to the processor and the data processing unit and configured for out-of-band management of the information handling system. The management controller may further be configured to obtain a hardware inventory and capabilities of the data processing unit; based on the hardware inventory and capabilities, generate a firmware capsule for execution during a basic input/output system phase of the data processing unit to cause a secure erasure of contents of a memory of the data processing unit; and communicate the firmware capsule to the data processing unit during an operating system phase of the data processing unit and cause the data processing unit to reboot to its basic input/output system phase in order to execute drivers of the firmware capsule in order to securely erase the memory.

Abstract: In interpreting a data record in a blockchain of a certain cryptographic asset, it is usually necessary to use the API of the node software provided by the developer of the software that devises the implementation method. However, since an input/output method of the API also differs depending on the implementation method, it is difficult to collect and analyze blockchain data of cryptographic assets according to a plurality of different implementation methods. The present invention provides a cryptographic asset blockchain processing apparatus or the like that collects blockchain data generated by a plurality of different implementation methods, converts the data into data that can be analyzed, and processes a transaction content such as a quantity, a unit price, and a partner of a transaction cryptographic asset into a standardized format, thereby improving convenience of analysis of a large amount of data for an accounting audit or the like.

Abstract: Systems and methods provide techniques for more effective and efficient proactive monitoring of a target software application framework. In response, embodiments of the present invention provide methods, apparatuses, systems, computing devices, and/or the like that are configured to enable effective and efficient proactive monitoring of a target software application framework using a load testing experiment definition data object, wherein the load testing experiment definition data object describes a load increase action definition, a steady state definition, and a fault inducement action definition.

Abstract: A baseboard management controller in an information handling system receives a human interface device input and converts the human interface device input into a human interface device scan code for storage at a human interface device descriptor buffer. The baseboard management controller determines whether or not the human interface device descriptor buffer is full and copying, when the human interface device descriptor buffer is full, the human interface scan codes in the human interface device descriptor buffer to a memory segment and sending an error code to a host system. The baseboard management controller also clears the human interface device descriptor buffer and re-populates the human interface device descriptor buffer with the human interface device scan code and the human interface device scan codes from the memory segment.