Patents by Inventor Jitendra Mohan

Jitendra Mohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250138757
    Abstract: A decoding engine within an integrated-circuit (IC) component executes a first plurality of error detection/correction operations with respect to first and second pluralities of data volumes to generate a corresponding first and second pluralities of error syndrome values. Each data volume of the first plurality of data volumes includes a first data block and a first error correction code together with a respective one of a plurality of unique q-bit metadata values, and each data volume of the second plurality of data volumes includes a second data block and a second error correction code together with a respective one of the plurality of unique q-bit metadata values. Output circuitry within the decoding engine selects one of the plurality of q-bit metadata values to be an output q-bit metadata value according to error-count differentiation indicated by the first and second pluralities of error syndrome values.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 1, 2025
    Inventors: Jitendra Mohan, Justina Provine, Anh T. Tran, Ken (Keqin) Han, Enrique Musoll
  • Patent number: 12277002
    Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.
    Type: Grant
    Filed: November 10, 2023
    Date of Patent: April 15, 2025
    Assignee: Astera Labs, Inc.
    Inventors: Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi
  • Patent number: 12277350
    Abstract: A decoding engine within an integrated-circuit (IC) component executes a first plurality of error detection/correction operations with respect to first and second pluralities of data volumes to generate a corresponding first and second pluralities of error syndrome values. Each data volume of the first plurality of data volumes includes a first data block and a first error correction code together with a respective one of a plurality of unique q-bit metadata values, and each data volume of the second plurality of data volumes includes a second data block and a second error correction code together with a respective one of the plurality of unique q-bit metadata values. Output circuitry within the decoding engine selects one of the plurality of q-bit metadata values to be an output q-bit metadata value according to error-count differentiation indicated by the first and second pluralities of error syndrome values.
    Type: Grant
    Filed: October 30, 2023
    Date of Patent: April 15, 2025
    Assignee: Astera Labs, Inc.
    Inventors: Jitendra Mohan, Justina Provine, Anh T. Tran, Ken (Keqin) Han, Enrique Musoll
  • Patent number: 12143288
    Abstract: A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: November 12, 2024
    Assignee: Astera Labs, Inc.
    Inventors: Casey Morrison, Enrique Musoll, Jitendra Mohan, Pulkit Khandelwal, Subbarao Arumilli, Vikas Khandelwal, Ken (Keqin) Han, Charan Enugala, Vivek Trivedi, Chi Feng
  • Publication number: 20240292839
    Abstract: The present provides a synergistic insecticidal composition comprising Chlorantraniliprole. Methoxy fenozide and at least one insecticidal compound selected from Deltamethrin or Lambda-Cyhalothrin. process of preparation of the composition and uses thereof.
    Type: Application
    Filed: February 22, 2022
    Publication date: September 5, 2024
    Inventors: Parikshit MUNDHRA, Jitendra MOHAN
  • Publication number: 20240237651
    Abstract: The present provides a synergistic insecticidal composition comprising Chlorantraniliprole, Spirotetramat and at least one insecticidal compound selected from Buprofezin, Bifenthrin, Propargite or Pyriproxyfen, process of preparation of the composition and uses thereof.
    Type: Application
    Filed: May 5, 2022
    Publication date: July 18, 2024
    Inventors: Parikshit MUNDHRA, Jitendra MOHAN
  • Publication number: 20240225000
    Abstract: The present provides a synergistic insecticidal composition comprising Chlorantraniliprole. Flubendiamide and at least one insecticidal compound selected from Pyriproxyfen. Diafenthiuron, Bifenthrin or Lambda-Cyhalothrin., process of preparation of the composition and uses thereof.
    Type: Application
    Filed: February 21, 2022
    Publication date: July 11, 2024
    Inventors: Parikshit MUNDHRA, Jitendra MOHAN
  • Publication number: 20240225001
    Abstract: The present invention provides a synergistic herbicidal composition comprising of phenylpyrazoline class of herbicide such as Pinoxaden, Triazinone class of herbicide such as Metribuzin and at least one herbicidal compound is selected from Isoproturon or Metsulfuron-methyl.
    Type: Application
    Filed: February 24, 2022
    Publication date: July 11, 2024
    Inventors: Parikshit MUNDHRA, Jitendra MOHAN
  • Publication number: 20240122183
    Abstract: The present provides a synergistic herbicidal composition comprising Pinoxaden, Carfentrazone-ethyl and at least one herbicidal compound selected from Fenoxaprop-p-ethyl or Isoproturon, and uses thereof.
    Type: Application
    Filed: February 25, 2022
    Publication date: April 18, 2024
    Inventors: Parikshit MUNDHRA, Jitendra MOHAN
  • Patent number: 11853115
    Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: December 26, 2023
    Assignee: Astera Labs, Inc.
    Inventors: Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi
  • Patent number: 11487317
    Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: November 1, 2022
    Assignee: Astera Labs, Inc.
    Inventors: Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi
  • Publication number: 20220295790
    Abstract: The present invention relates to a synergistic fungicidal composition comprising a strobilurin based compound, validamycin and a compound A compound selected from the group comprising thifluzamide, hexaconazole, propiconazole, tricyclazole and difenoconazole. The composition of the present invention decreases application rates of each of the active ingredients and is non-phytotoxic.
    Type: Application
    Filed: June 15, 2020
    Publication date: September 22, 2022
    Applicants: JDM SCIENTIFIC RESEARCH ORGANISATION PRIVATE LIMITED, SUMISHO AGRO INDIA PVT. LTD.
    Inventors: Parikshit MUNDHRA, Jitendra MOHAN
  • Patent number: 11327913
    Abstract: Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 10, 2022
    Assignee: Astera Labs, Inc.
    Inventors: Casey Morrison, Charan Enugala, Chi Feng, Enrique Musoll, Jitendra Mohan, Ken (Keqin) Han, Pulkit Khandelwal, Subbarao Arumilli, Vikas Khandelwal, Vivek Trivedi
  • Patent number: 11258696
    Abstract: A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: February 22, 2022
    Assignee: Asiera Labs, Inc.
    Inventors: Casey Morrison, Enrique Musoll, Jitendra Mohan, Pulkit Khandelwal, Subbarao Arumilli, Vikas Khandelwal, Ken (Keqin) Han, Charan Enugala, Vivek Trivedi, Chi Feng
  • Patent number: 11150687
    Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: October 19, 2021
    Assignee: Astera Labs, Inc.
    Inventors: Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi
  • Patent number: 8873592
    Abstract: A system and method is disclosed for adding a low data rate data channel to a 100Base-T Ethernet link without significantly impacting an IEEE defined 100Base-T protocol for the Ethernet link. A dual data channel transmitter encodes a high data rate data stream in an MLT-3 encoder and encodes a low data rate data stream using bit representations that are not valid bit representations in the MLT-3 encoder. The dual data channel transmitter transmits both of the encoded bit streams in a dual data stream. A dual data channel receiver receives the dual data stream and separates and decodes the two bit streams. A low data rate data channel is provided in conjunction with a high data rate data channel without significantly impacting the operation of the high data rate data channel.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: October 28, 2014
    Assignee: National Semiconductor Corporation
    Inventor: Jitendra Mohan
  • Patent number: 8638125
    Abstract: A low voltage differential signal (LVDS) driver circuit with reduced power consumption. A pre-driver stage, implemented as a differential current mode amplifier, is driven by the differential input signal and provides a corresponding differential drive signal, which drives the output stage, implemented as a differential voltage mode amplifier, which, in turn, provides the differential output signal for the load. Total current consumption equals the load current, which is provided by the output stage, plus a much smaller current used by the pre-driver stage.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: January 28, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Khaldoon Abugharbieh, Jitendra Mohan, Ivan Duzevik
  • Publication number: 20110234318
    Abstract: A low voltage differential signal (LVDS) driver circuit with reduced power consumption. A pre-driver stage, implemented as a differential current mode amplifier, is driven by the differential input signal and provides a corresponding differential drive signal, which drives the output stage, implemented as a differential voltage mode amplifier, which, in turn, provides the differential output signal for the load. Total current consumption equals the load current, which is provided by the output stage, plus a much smaller current used by the pre-driver stage.
    Type: Application
    Filed: June 14, 2011
    Publication date: September 29, 2011
    Applicant: National Semiconductor Corporation
    Inventors: Khaldoon Abugharbieh, Jitendra Mohan, Ivan Dyzevik
  • Patent number: 7800411
    Abstract: A system and method is disclosed for providing a strobed comparator with reduced offset and reduced charge kickback. The strobed comparator circuit comprises a differential pair of transistors coupled to a first switch circuit, a regenerative latch circuit, a first strobe signal line coupled to the switch circuit and a second strobe signal line coupled to the regenerative latch circuit. The first and second strobe signal lines provide separate strobe controls. The differential pair of transistors reduces the charge kickback effect by remaining in an “on” state. The differential pair of transistors is enabled when the regenerative latch circuit is in a reset condition and the regenerative latch circuit is enabled when the differential pair of transistors is in a saturation condition.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: September 21, 2010
    Assignee: National Semiconductor Corporation
    Inventor: Jitendra Mohan
  • Patent number: 7630422
    Abstract: A driver for a vertical-cavity surface emitting laser (VCSEL) is provided that includes a bias current source, a modulation current source, and an output tracking circuit. The bias current source is operable to generate a bias current and an output voltage for the VCSEL and to generate a replica output voltage. The modulation current source is coupled to the bias current source by at least one switch and is operable to generate a modulation current for the VCSEL when the switch is closed. The output tracking circuit is coupled to the bias current source. The output tracking circuit is operable to generate a feedback signal for the bias current source based on the output voltage and the replica output voltage. The bias current source is also operable to generate the output voltage and the replica output voltage based on the feedback signal.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: December 8, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Ramsin M. Ziazadeh, Jitendra Mohan