Abstract: A decoding engine within an integrated-circuit (IC) component executes a first plurality of error detection/correction operations with respect to first and second pluralities of data volumes to generate a corresponding first and second pluralities of error syndrome values. Each data volume of the first plurality of data volumes includes a first data block and a first error correction code together with a respective one of a plurality of unique q-bit metadata values, and each data volume of the second plurality of data volumes includes a second data block and a second error correction code together with a respective one of the plurality of unique q-bit metadata values. Output circuitry within the decoding engine selects one of the plurality of q-bit metadata values to be an output q-bit metadata value according to error-count differentiation indicated by the first and second pluralities of error syndrome values.

Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Abstract: A decoding engine within an integrated-circuit (IC) component executes a first plurality of error detection/correction operations with respect to first and second pluralities of data volumes to generate a corresponding first and second pluralities of error syndrome values. Each data volume of the first plurality of data volumes includes a first data block and a first error correction code together with a respective one of a plurality of unique q-bit metadata values, and each data volume of the second plurality of data volumes includes a second data block and a second error correction code together with a respective one of the plurality of unique q-bit metadata values. Output circuitry within the decoding engine selects one of the plurality of q-bit metadata values to be an output q-bit metadata value according to error-count differentiation indicated by the first and second pluralities of error syndrome values.

Abstract: A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.

Abstract: The present provides a synergistic insecticidal composition comprising Chlorantraniliprole. Methoxy fenozide and at least one insecticidal compound selected from Deltamethrin or Lambda-Cyhalothrin. process of preparation of the composition and uses thereof.

Abstract: The present provides a synergistic insecticidal composition comprising Chlorantraniliprole, Spirotetramat and at least one insecticidal compound selected from Buprofezin, Bifenthrin, Propargite or Pyriproxyfen, process of preparation of the composition and uses thereof.

Abstract: The present provides a synergistic insecticidal composition comprising Chlorantraniliprole. Flubendiamide and at least one insecticidal compound selected from Pyriproxyfen. Diafenthiuron, Bifenthrin or Lambda-Cyhalothrin., process of preparation of the composition and uses thereof.

Abstract: The present invention provides a synergistic herbicidal composition comprising of phenylpyrazoline class of herbicide such as Pinoxaden, Triazinone class of herbicide such as Metribuzin and at least one herbicidal compound is selected from Isoproturon or Metsulfuron-methyl.

Abstract: The present provides a synergistic herbicidal composition comprising Pinoxaden, Carfentrazone-ethyl and at least one herbicidal compound selected from Fenoxaprop-p-ethyl or Isoproturon, and uses thereof.

Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Abstract: The present invention relates to a synergistic fungicidal composition comprising a strobilurin based compound, validamycin and a compound A compound selected from the group comprising thifluzamide, hexaconazole, propiconazole, tricyclazole and difenoconazole. The composition of the present invention decreases application rates of each of the active ingredients and is non-phytotoxic.

Abstract: Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.

Abstract: A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.

Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Abstract: A system and method is disclosed for adding a low data rate data channel to a 100Base-T Ethernet link without significantly impacting an IEEE defined 100Base-T protocol for the Ethernet link. A dual data channel transmitter encodes a high data rate data stream in an MLT-3 encoder and encodes a low data rate data stream using bit representations that are not valid bit representations in the MLT-3 encoder. The dual data channel transmitter transmits both of the encoded bit streams in a dual data stream. A dual data channel receiver receives the dual data stream and separates and decodes the two bit streams. A low data rate data channel is provided in conjunction with a high data rate data channel without significantly impacting the operation of the high data rate data channel.

Abstract: A low voltage differential signal (LVDS) driver circuit with reduced power consumption. A pre-driver stage, implemented as a differential current mode amplifier, is driven by the differential input signal and provides a corresponding differential drive signal, which drives the output stage, implemented as a differential voltage mode amplifier, which, in turn, provides the differential output signal for the load. Total current consumption equals the load current, which is provided by the output stage, plus a much smaller current used by the pre-driver stage.

Abstract: A low voltage differential signal (LVDS) driver circuit with reduced power consumption. A pre-driver stage, implemented as a differential current mode amplifier, is driven by the differential input signal and provides a corresponding differential drive signal, which drives the output stage, implemented as a differential voltage mode amplifier, which, in turn, provides the differential output signal for the load. Total current consumption equals the load current, which is provided by the output stage, plus a much smaller current used by the pre-driver stage.

Abstract: A system and method is disclosed for providing a strobed comparator with reduced offset and reduced charge kickback. The strobed comparator circuit comprises a differential pair of transistors coupled to a first switch circuit, a regenerative latch circuit, a first strobe signal line coupled to the switch circuit and a second strobe signal line coupled to the regenerative latch circuit. The first and second strobe signal lines provide separate strobe controls. The differential pair of transistors reduces the charge kickback effect by remaining in an “on” state. The differential pair of transistors is enabled when the regenerative latch circuit is in a reset condition and the regenerative latch circuit is enabled when the differential pair of transistors is in a saturation condition.

Abstract: A driver for a vertical-cavity surface emitting laser (VCSEL) is provided that includes a bias current source, a modulation current source, and an output tracking circuit. The bias current source is operable to generate a bias current and an output voltage for the VCSEL and to generate a replica output voltage. The modulation current source is coupled to the bias current source by at least one switch and is operable to generate a modulation current for the VCSEL when the switch is closed. The output tracking circuit is coupled to the bias current source. The output tracking circuit is operable to generate a feedback signal for the bias current source based on the output voltage and the replica output voltage. The bias current source is also operable to generate the output voltage and the replica output voltage based on the feedback signal.