Abstract: There is disclosed high-speed current-mirror circuitry and methods of operating the same. An exemplary impedance-peaking current mirror comprises a N-channel drive transistor and a N-channel mirror transistor. The N-channel drive transistor has a source coupled to ground, a drain coupled to a current source and a gate coupled to the drain via a series connection of a resistor and an inductor. The N-channel mirror transistor has a source coupled to ground, a gate coupled to the drain of the N-channel drive transistor, and a drain coupled to a positive power supply via an impedance load.

Abstract: There is disclosed a comparator comprising: 1) a first comparison circuit capable of receiving an input signal, wherein the first comparison circuit is enabled and compares the signal when a received LATCH signal is enabled and is disabled when the received LATCH signal is disabled; and 2) a second comparison circuit coupled to the input signal in parallel with the first comparison circuit, wherein an input stage of the second comparison circuit is substantially identical to an input stage of the first comparison circuit. The second comparison circuit is enabled and compares the input signal when the received LATCH is signal is disabled and is disabled when the received LATCH signal is enabled.

Abstract: A low power analog equalizer is disclosed that provides up to twenty decibels (20 dB) of alternating current gain in a single stage of analog signal equalization. The analog equalizer comprises an operational amplifier coupled to two half circuits. Each half circuit comprises an impedance network capable of receiving an analog input voltage and generating a current signal that is inversely proportional to frequency, a variable resistor capable of adjusting the gain of the operational amplifier, and a transistor and an amplifier coupled in a cascode configuration to create a low impedance node at the output of the impedance network. The analog equalizer is fabricated with 0.18 micron CMOS technology and operates at 1.8 volts.

Abstract: There is disclosed an amplifier for operating from a power supply having a first voltage level. The amplifier comprises: 1) a plurality of thick-oxide field effect transistors, each of the plurality of thick-oxide field effect transistors having a relatively thick oxide layer and fabricated using a first process such that the each thick-oxide field effect transistor can withstand a gate-to-source difference, a gate-to-drain difference, and a gate-to-bulk difference at least equal to a first maximum operating voltage, wherein the first.

Abstract: An RC calibration circuit, which utilizes a resistor and a variable capacitor connected in parallel, reduces power consumption and increases the accuracy of the calibration by comparing the voltage on the resistor to the voltage on the capacitor after a predetermined time has expired since the capacitor began charging up. The result of the comparison, which indicates whether the voltage on the resistor is greater than the voltage on the capacitor, is then used to adjust the capacitance of the capacitor to servo the RC time constant to a predetermined value.

Abstract: A line driver outputs a pair of transmit signals TX+ and TX− that have substantially reduced output level variations due to variations in process, voltage, and temperature. The reduced output level variations are provided by varying the magnitude of the current that sets up the voltages of the transmit signals in a manner that offsets variations in the power supply voltage, temperature, and process, and by limiting variations of the bandgap current source to process and temperature only.

Abstract: A line driver circuit capable of operating in 100Base-T mode and 10Base-T mode includes a 1:1 transformer having a primary winding, the primary winding having a center tap. A current source couples to the center tap. A current steering circuit steers drive current from the current source in first and second directions to provide a differential output signal at the output nodes. The current steering circuit includes two switches. Input signals control the opening and closing of the switches such that the switches are never both open at the same time. Thus, during a time period, one switch closes to pull one output node up toward the supply voltage, while the other switch opens to pull the other output node down toward circuit ground. Since the current source couples to the center tap of the transformer, the current source is only pulled down to a voltage half that of the supply voltage rather than to circuit ground. Therefore, the current source has sufficient headroom to drive the output current.

Abstract: A calibration circuit adjusts a differential output voltage from a line driver circuit when the differential output voltage falls outside a specified tolerance range. The calibration circuit includes a sample and hold circuit which samples the differential output voltage and holds a representative signal. A comparator compares the held signal with a reference voltage signal. When the held signal is greater than the reference voltage signal the comparator outputs a LOW signal and when the held signal is less than the reference voltage signal the comparator outputs a HIGH signal. The comparator output signal is stored in a memory circuit of a control logic. The control logic instructs an up/down counter to increment when the comparator output is LOW and to decrement when the comparator output is HIGH. A calibration current source sinks a unit of calibration current when the comparator output is LOW and sources a unit of calibration current when the comparator output is HIGH.

Abstract: A signal shaping circuit for use in a transmission line driver and the like is disclosed. The input is pulse signal having a rising edge that triggers a delay circuit which produces a first sequence of multiple delayed outputs and a falling edge which triggers the delay circuit to produce a second sequence of multiple delayed outputs. Transition control circuitry is included which operates to control the transition time of the output signal in a first direction, such as the rise time, in response to the first sequence of multiple delayed outputs and to control the transition time of the output signal in a second direction, such as the fall time, in response to the second sequence of multiple delayed outputs. By controlling the first and second delayed output, the rise and fall times of the output signal can be precisely controlled.

Abstract: A current amplifier driver capable of driving both 10 Base-T signalling and 100 Base signalling in a Local Area Network (LAN) includes one constant current source. A voltage controlled switch is contained in each of four vertical segment of an H-bridge circuit. Two voltage signals are applied to the switches to control the direction of current from a constant current source across a load. When one of the voltage signals is high, the other is low and two switches of the four switches turn on. The current amplifier driver sinks the constant current in a first direction, such that a voltage drop across the output nodes is positive. When the other voltage signal is high the switches that were on turn off, and the other two switches turn on to sink the constant current across the load in the opposite direction, such that a voltage drop across the output nodes is negative. When both voltage signals are low, all four switches turn off, and the output voltage is zero.

Abstract: A stacked current mirror circuit includes four N-channel MOS transistors. One transistor serves as an input device for conducting via its drain, a majority of the reference current. Another transistor is connected as a mirroring device, with its drain coupled to a voltage source, its gate coupled to the gate of the input device, and its source coupled to the source of the input device at a first common node. These two transistors couple to form a first current mirror circuit which couples to the input of a second current mirror comprising the third and fourth transistors. The drain and gate of the third transistor couple to the first common node and the gate of the fourth transistor. The sources of both the third and fourth transistors couple to a second common node (e.g., ground), and the drain of the fourth transistor provides the output. As a result, current is mirrored from the input device transistor to the mirroring device transistor, and then forced through the third transistor.

Abstract: A current mode driver capable of driving both 10 Base-T signalling and 100 Base-T signalling in a Local Area Network (LAN) includes two or four current sources. In a first embodiment, a differential signal generator drives four current sources. The generator outputs four signals, one of which is received by each current source. Using these signals, two of the current sources push or pull current across the load in one direction, while the other two current sources push or pull current across the load in the other direction, such that a full differential signal is generated across the load. In another embodiment, a signal generator drives two current sources which drive into the load one at a time. Two switches provide either high resistance or low resistance during half of a signal cycle such that current is pulled through the load in one direction, and prevented from flowing through the load in the other direction.