Abstract: In accordance with some embodiments of the present invention, a gas sensor system is disclosed. In accordance with some embodiments, a system includes a glass substrate; a heater formed on the glass substrate; and a sensor formed adjacent the heater formed on the glass substrate. A method of forming a gas sensor system according to some embodiments includes providing a glass substrate; forming a heater on the glass substrate; and forming a sensor adjacent the heater on the glass substrate.

Abstract: A method for verifying data integrity of a block device is provided. The method includes providing a secure world execution environment configured to monitor changes to data blocks of a block device, within the secure world execution environment, generating a hash for changed data blocks of the block device, and within the secure world execution environment, verifying and generating a cryptographic signature.

Abstract: A packaged integrated circuit includes an integrated circuit substrate and a cap bonded to a surface of the integrated circuit substrate. The cap has a recess therein that is at least partially lined with at least one segment of an inductor. This inductor may be electrically coupled to an electrical component within the integrated circuit substrate. In some embodiments, the inductor is patterned to extend along a sidewall and interior top surface of the recess, which extends opposite the integrated circuit substrate. The inductor may include a plurality of arcuate-shaped segments and may be patterned to be symmetric about a center-tapped portion thereof. The cap may also include a magnetic material therein that increases an effective inductance of the inductor relative to an otherwise equivalent cap and inductor combination that is devoid of the magnetic material.

Abstract: An integrated circuit (342) that is electrically connected to a printed circuit board (246) with a package substrate (344) includes a circuit body (352), and a bump array (354) that electrically connects the circuit body (352) to the package substrate (244). The bump array (354) includes a first bump set (356) having a plurality of signal bumps (364) and a plurality of non-signal bumps (366) alternatingly interspersed and aligned along an axis. With the present design, the bump array (354) allows each signal bump (364) to be surrounded by a power bump (370) and a ground bump (368). The package substrate (344) includes (i) a package body (372); and (ii) a pin array (374) that includes a first pin set (376) that includes a plurality of signal pins (384) and a plurality of non-signal pins (386) alternatingly interspersed and aligned along an axis.

Abstract: A method for verifying data integrity of a block device is provided. The method includes providing a secure world execution environment configured to monitor changes to data blocks of a block device, within the secure world execution environment, generating a hash for changed data blocks of the block device, and within the secure world execution environment, verifying and generating a cryptographic signature.

Abstract: A test assembly (12) for testing a device (10) having a heat spreader (20), a package substrate (18) having a substrate ground (18G), and a grounding conductive segment (44A), includes (i) an input conductive segment (38) that is electrically connected to the heat spreader (20), (ii) a test board (28) having a board ground (30), and (iii) a control system (34) that is electrically coupled to the input conductive segment (38) and the board ground (30). During testing, the device (10) is positioned so that the substrate ground (18G) is electrically connected to the board ground (30). Additionally, the control system (34) directs a test current to one of the input conductive segment (38) and the board ground (30) to test the effectiveness of the grounding conductive segment (44A) including a first electrical interface (45A).

Abstract: A test assembly (12) for testing a device (10) having a heat spreader (20), a package substrate (18) having a substrate ground (18G), and a grounding conductive segment (44A), includes (i) an input conductive segment (38) that is electrically connected to the heat spreader (20), (ii) a test board (28) having a board ground (30), and (iii) a control system (34) that is electrically coupled to the input conductive segment (38) and the board ground (30). During testing, the device (10) is positioned so that the substrate ground (18G) is electrically connected to the board ground (30). Additionally, the control system (34) directs a test current to one of the input conductive segment (38) and the board ground (30) to test the effectiveness of the grounding conductive segment (44A) including a first electrical interface (45A).

Abstract: A combination for electrically connecting an integrated circuit (14) to a lead frame package (18) comprises a first jumper chip (16) and a plurality of bonding wires (20) including at least a first bonding wire and a second bonding wire. The first bonding wire extends between and electrically connects the first jumper chip (16) and the lead frame package (18). Additionally, the second bonding wire extends between and electrically connects the first jumper chip (16) and the integrated circuit (14). The plurality of bonding wires (20) can further include a third bonding wire that extends between and electrically connects the integrated circuit (14) and the lead frame package (18). Further, the combination can also comprise a second jumper chip (216B), and the plurality of bonding wires (20) can further include a third bonding wire and a fourth bonding wire. The third bonding wire can extend between and electrically connect the second jumper chip (216B) and the lead frame package (18).

Abstract: A lead frame package is disclosed where transmission signals are coupled into a die from a pair of lead frames through bonding wires that are separated by no more than three times a diameter of one of the bonding wires. In some embodiments, pairs of lead frames carrying differential transmission signals can be shielded by adjacent pairs of ground and power leads that are coupled into the die through bonding wires that are also separated by no more than three times a diameter of one of the bonding wires.

Abstract: An integrated circuit (342) that is electrically connected to a printed circuit board (246) with a package substrate (344) includes a circuit body (352), and a bump array (354) that electrically connects the circuit body (352) to the package substrate (244). The bump array (354) includes a first bump set (356) having a plurality of signal bumps (364) and a plurality of non-signal bumps (366) alternatingly interspersed and aligned along an axis. With the present design, the bump array (354) allows each signal bump (364) to be surrounded by a power bump (370) and a ground bump (368). The package substrate (344) includes (i) a package body (372); and (ii) a pin array (374) that includes a first pin set (376) that includes a plurality of signal pins (384) and a plurality of non-signal pins (386) alternatingly interspersed and aligned along an axis.

Abstract: A package (216) for electrically connecting an integrated circuit (212) to a printed circuit board (214) includes a mount array (219) and a substrate body (216A). The mount array (219) is electrically connected to the integrated circuit (212). The mount array (219) includes a plurality of positive terminal mounts (342), a plurality of negative terminal mounts (344), and a plurality of signal mounts (346). The substrate body (216A) includes a first conductive layer (220a), a second conductive layer (220b), and an insulating layer (222a) that is positioned between the first conductive layer (220a) and the second conductive layer (220b). The first conductive layer (220a) includes (i) a terminal portion (350) that is connected one of the terminal mounts (342) (344), and (ii) a signal portion (352) that is connected to the signal mounts (346). Further, the second conductive layer (220b) is directly connected to the other of the terminal mounts (344) (342).

Abstract: A multi-package module that includes a multi-layer interconnect structure, a housing structure attached to the multi-layer interconnect structure, and a plurality of integrated circuit packages inserted into slots in the housing structure, and placed into contact with the multi-layer interconnect structure. The integrated circuit packages can be removed from the slots in the housing structure, thereby enabling testing and/or replacement of the integrated circuit packages.

Abstract: A lead frame package is disclosed where transmission signals are coupled into a die from a pair of lead frames through bonding wires that are separated by no more than three times a diameter of one of the bonding wires. In some embodiments, pairs of lead frames carrying differential transmission signals can be shielded by adjacent pairs of ground and power leads that are coupled into the die through bonding wires that are also separated by no more than three times a diameter of one of the bonding wires.

Abstract: A package substrate (16) for electrically connecting an integrated circuit (12) to a printed circuit board (14) includes a core (222c), a patterned conductive layer (220c), a plurality of spaced apart, discrete capacitors (230), and an insulating layer (222b). The patterned conductive layer (220c) is positioned on the core (222c). The discrete capacitors (230) are electrically connected to the patterned conductive layer (220c). The insulating layer (222b) covers the patterned conductive layer (220c) and separates the capacitors (230). The capacitors (230) are positioned to provide a relatively low impedance path for quick access to power to stabilize the voltage delivered to the integrated circuit (12), and the capacitors (230) do not occupy valuable space on the integrated circuit (12), and the printed circuit board (14).

Abstract: A multi-package module that includes a multi-layer interconnect structure, a housing structure attached to the multi-layer interconnect structure, and a plurality of integrated circuit packages inserted into slots in the housing structure, and placed into contact with the multi-layer interconnect structure. The integrated circuit packages can be removed from the slots in the housing structure, thereby enabling testing and/or replacement of the integrated circuit packages.

Abstract: A package (16) for electrically connecting one or more integrated circuits (12) to a printed circuit board (14) includes a substrate body (16A), a pinout (16B), and a support assembly (18). The substrate body (16A) includes at least one insulating layer (222), and at least one patterned conductive layer (220) that is electrically connected to the integrated circuit (12) and the printed circuit board (14). The pinout (16B) extends between the substrate body (16A) and the printed circuit board (14), and the pinout (16B) electrically and mechanically connects the substrate body (16A) to the printed circuit board (14). The support assembly (18) includes at least one support (38) that extends between the substrate body (16A) and the printed circuit board (14) to support the substrate body (16A) relative to the printed circuit board (14). The support (38) includes a passive electrical component (19) that is electrically connected to the at least one patterned conductive layer (220).

Abstract: A package (216) for electrically connecting an integrated circuit (212) to a printed circuit board (214) includes a mount array (219) and a substrate body (216A). The mount array (219) is electrically connected to the integrated circuit (212). The mount array (219) includes a plurality of positive terminal mounts (342), a plurality of negative terminal mounts (344), and a plurality of signal mounts (346). The substrate body (216A) includes a first conductive layer (220a), a second conductive layer (220b), and an insulating layer (222a) that is positioned between the first conductive layer (220a) and the second conductive layer (220b). The first conductive layer (220a) includes (i) a terminal portion (350) that is connected one of the terminal mounts (342) (344), and (ii) a signal portion (352) that is connected to the signal mounts (346). Further, the second conductive layer (220b) is directly connected to the other of the terminal mounts (344) (342).

Abstract: A package substrate (16) for electrically connecting an integrated circuit (12) to a printed circuit board (14) includes a core (222c), a patterned conductive layer (220c), a plurality of spaced apart, discrete capacitors (230), and an insulating layer (222b). The patterned conductive layer (220c) is positioned on the core (222c). The discrete capacitors (230) are electrically connected to the patterned conductive layer (220c). The insulating layer (222b) covers the patterned conductive layer (220c) and separates the capacitors (230). The capacitors (230) are positioned to provide a relatively low impedance path for quick access to power to stabilize the voltage delivered to the integrated circuit (12), and the capacitors (230) do not occupy valuable space on the integrated circuit (12), and the printed circuit board (14).

Abstract: An integrated circuit package (212) for electrically connecting an integrated circuit (216) to a substrate (214) includes a package assembly (218) having an outer periphery (324) and a pinout (220) that includes a first pin array (334), a second pin array (336) and a third pin array (338). The first pin array (334) includes a plurality of consecutively positioned signal pins (322S). The second pin array (336) includes a plurality of power pins (322P) and ground pins (322G) interspersed with one another. The second pin array (336) is positioned nearer the outer periphery (324) than the first pin array (334). The third pin array (338) includes a plurality of consecutively positioned signal pins (322S) and is positioned nearer the outer periphery (324) than the second pin array (336).

Abstract: A package for a flip-chip integrated circuit device and a packaged flip-chip integrated circuit device that include ground strips and power strips disposed on the top surface of the package substrate. Decoupling capacitors are disposed over and electrically coupled to a ground strip and are disposed over and electrically coupled to a power strip. Microvias electrically couple the power strips to a power plane and electrically couple the ground strip to a ground plane. Each power strip and ground strip extend within a die attach region of the package substrate such that a semiconductor die can be bonded thereto for coupling power and ground between the semiconductor die and the decoupling capacitors. The power strip and ground strip provide low impedance pathways between the flip-chip semiconductor die and the decoupling capacitors. Thereby, effective decoupling capacitance is provided that is suitable for high frequency applications.