Abstract: The embodiments of the disclosure provide a FinFET. The FinFET includes a substrate, a first gate stack and a second gate stack. The substrate has a first fin and a second fin. The first gate stack is across the first fin and extends along a widthwise direction of the first fin. The second gate stack is across the second fin and extends along a widthwise direction of the second fin. A bottommost surface of the first gate stack is lower than a bottommost surface of the second gate stack, and a first gate height of the first gate stack directly on the first fin is substantially equal to a second gate height of the second gate stack directly on the second fin.

Abstract: A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.

Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.

Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.

Abstract: The present disclosure provides methods of forming semiconductor devices. A method according to the present disclosure includes receiving a workpiece that includes a stack of semiconductor layers, depositing a first pad oxide layer on a germanium-containing top layer of the stack, depositing a second pad oxide layer on the first pad oxide layer, depositing a pad nitride layer on the second pad oxide layer, and patterning the stack using the first pad oxide layer, the second pad oxide layer, and the pad nitride layer as a hard mask layer. The depositing of the first pad oxide layer includes a first oxygen plasma power and the depositing of the second pad oxide layer includes a second oxygen plasma power greater than the first oxygen plasma power.

Abstract: Methods and associated devices including the fabrication of a semiconductor structure are described that include epitaxially growing a stack of layers alternating between a first composition and a second composition. The stack of layers extends across a first region and a second region of a semiconductor substrate. The stack of layers in the second region of the semiconductor substrate may be etched to form an opening. A passivation process is then performed that includes introducing chlorine to at least one surface of the opening. After performing the passivation process, an epitaxial liner layer is grown in the opening.

Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.

Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.

Abstract: Methods and associated devices including the fabrication of a semiconductor structure are described that include epitaxially growing a stack of layers alternating between a first composition and a second composition. The stack of layers extends across a first region and a second region of a semiconductor substrate. The stack of layers in the second region of the semiconductor substrate may be etched to form an opening. A passivation process is then performed that includes introducing chlorine to at least one surface of the opening. After performing the passivation process, an epitaxial liner layer is grown in the opening.

Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.

Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.

Abstract: The present disclosure provides methods of forming semiconductor devices. A method according to the present disclosure includes receiving a workpiece that includes a stack of semiconductor layers, depositing a first pad oxide layer on a germanium-containing top layer of the stack, depositing a second pad oxide layer on the first pad oxide layer, depositing a pad nitride layer on the second pad oxide layer, and patterning the stack using the first pad oxide layer, the second pad oxide layer, and the pad nitride layer as a hard mask layer. The depositing of the first pad oxide layer includes a first oxygen plasma power and the depositing of the second pad oxide layer includes a second oxygen plasma power greater than the first oxygen plasma power.

Abstract: A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T1 of the cap portion is greater than a thickness T2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.

Abstract: Methods and associated devices including the fabrication of a semiconductor structure are described that include epitaxially growing a stack of layers alternating between a first composition and a second composition. The stack of layers extends across a first region and a second region of a semiconductor substrate. The stack of layers in the second region of the semiconductor substrate may be etched to form an opening. A passivation process is then performed that includes introducing chlorine to at least one surface of the opening. After performing the passivation process, an epitaxial liner layer is grown in the opening.

Abstract: Methods of rectifying a sidewall profile of a fin-shaped stack structure are provided. An example method includes forming, on a substrate, a first fin-shaped structure and a second fin-shaped structure each including a plurality of channel layers interleaved by a plurality of sacrificial layers; depositing a first silicon liner over the first fin-shaped structure and the second fin-shaped structure; depositing a dielectric layer over the substrate, the first fin-shaped structure and the second fin-shaped structure; etching back the dielectric layer to form an isolation feature between the first fin-shaped structure and the second fin-shaped structure and to remove the first silicon liner over the first fin-shaped structure and the second fin-shaped structure to expose sidewalls of the plurality of channel layers and the plurality of sacrificial layers, and epitaxially depositing a second silicon liner over the exposed sidewalls of the plurality of channel layers and the plurality of sacrificial layers.

Abstract: Methods of rectifying a sidewall profile of a fin-shaped stack structure are provided. An example method includes forming, on a substrate, a first fin-shaped structure and a second fin-shaped structure each including a plurality of channel layers interleaved by a plurality of sacrificial layers; depositing a first silicon liner over the first fin-shaped structure and the second fin-shaped structure; depositing a dielectric layer over the substrate, the first fin-shaped structure and the second fin-shaped structure; etching back the dielectric layer to form an isolation feature between the first fin-shaped structure and the second fin-shaped structure and to remove the first silicon liner over the first fin-shaped structure and the second fin-shaped structure to expose sidewalls of the plurality of channel layers and the plurality of sacrificial layers, and epitaxially depositing a second silicon liner over the exposed sidewalls of the plurality of channel layers and the plurality of sacrificial layers.

Abstract: A method includes depositing a dummy semiconductor layer and a first semiconductor layer over a substrate, forming spacers on sidewalls of the dummy semiconductor layer, forming a first epitaxial material in the substrate, exposing the dummy semiconductor layer and the first epitaxial material, where exposing the dummy semiconductor layer and the first epitaxial material includes thinning a backside of the substrate, etching the dummy semiconductor layer to expose the first semiconductor layer, where the spacers remain over and in contact with end portions of the first semiconductor layer while etching the dummy semiconductor layer, etching portions of the first semiconductor layer using the spacers as a mask, and replacing a second epitaxial material and the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of a first transistor.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a stack over a substrate. The stack includes alternating first semiconductor layers and second semiconductor layers. The method also includes forming a polishing stop layer over the stack and a dummy layer over the polishing stop layer, recessing the dummy layer, the polishing stop layer and the stack to form a recess, forming a third semiconductor layer to fill the recess, and planarizing the dummy layer and the third semiconductor layer until the polishing stop layer is exposed. The method also includes patterning the polishing stop layer and the stack into a first fin structure and the third semiconductor layer into a second fin structure, removing the second semiconductor layers of the first fin structure to form nanostructures, and forming a gate stack across the first fin structure and the second fin structure.

Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.

Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.