Patents by Inventor Jiwei Lu

Jiwei Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11207008
    Abstract: The present disclosure provides a system and method for analyzing a physiological parameter of a vital sign signal. The method may include acquiring a vital sign signal, storing data, computing and analyzing, processing, and outputting a result. The system may compute and analyze the physiological parameter of the vital sign signal, especially a blood oxygen saturation, via a plurality of algorithms, judge or process the computation result, and output the judgment result.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: December 28, 2021
    Assignee: VITA-COURSE TECHNOLOGIES (HAINAN) CO., LTD.
    Inventors: Ying Lu, Chuanmin Wei, Jiwei Zhao, Heng Peng, Ziming Deng, Zijian Huang, Zhiyong Wang
  • Patent number: 11048516
    Abstract: Systems, methods, and apparatuses for last branch record support are described. In an embodiment, a hardware processor core comprises a hardware execution unit to execute a branch instruction, at least two last branch record (LBR) registers to store a source and destination information of a branch taken during program execution, wherein an entry in a LBR register is to include an encoding of the branch, a write bit array to indicate which LBR register is architecturally correct, an architectural bit array to indicate when an LBR register has been written, and a plurality of top of stack pointers to indicate which LBR register in a LBR register stack is to be written.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Paul Caprioli, Koichi Yamada, Jason M. Agron, Jiwei Lu
  • Publication number: 20200319914
    Abstract: A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.
    Type: Application
    Filed: April 28, 2020
    Publication date: October 8, 2020
    Inventors: Keqiang WU, Jiwei LU, Koichi YAMADA, Yong-Fong LEE
  • Patent number: 10789056
    Abstract: Technologies for binary translation include a computing device that allocates a translation cache shared by all threads associated with a corresponding execution domain. The computing device assigns a thread to an execution domain, translates original binary code of the thread to generate translated binary code, and installs the translated binary code into the corresponding translation cache for execution. The computing device may allocate a global region cache, generate region metadata associated with the original binary code of a thread, and store the region metadata in the global region cache. The original binary code may be translated using the region metadata. The computing device may allocate a global prototype cache, translate the original binary code of a thread to generate prototype code, and install the prototype code in the global prototype cache. The prototype code may be a non-executable version of the translated binary code. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Koichi Yamada, Jose A. Baiocchi Paredes, Abhik Sarkar, Ajay Harikumar, Jiwei Lu
  • Patent number: 10642644
    Abstract: Methods, apparatus, and system to identify a memory contention with respect to a process, re-write the process to form a transactional process, and execute the transactional process in a speculative execution.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Keqiang Wu, Jiwei Lu, Koichi Yamada, Yong-Fong Lee
  • Patent number: 10114643
    Abstract: Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for a target address of a branch instruction associated with a translated portion of a routine in a table comprising valid target addresses. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Koichi Yamada, Palanivelra Shanmugavelayutham, Arvind Krishnaswamy, Jason M. Agron, Jiwei Lu
  • Patent number: 9990233
    Abstract: Technologies for partial binary translation on multi-core platforms include a shared translation cache, a binary translation thread scheduler, a global installation thread, and a local translation thread and analysis thread for each processor core. On detection of a hotspot, the thread scheduler first resumes the global thread if suspended, next activates the global thread if a translation cache operation is pending, and last schedules local translation or analysis threads for execution. Translation cache operations are centralized in the global thread and decoupled from analysis and translation. The thread scheduler may execute in a non-preemptive nucleus, and the translation and analysis threads may execute in a preemptive runtime. The global thread may be primarily preemptive with a small non-preemptive nucleus to commit updates to the shared translation cache. The global thread may migrate to any of the processor cores. Forward progress is guaranteed. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Abhik Sarkar, Jiwei Lu, Palanivelrajan Rajan Shanmugavelayutham, Jason M. Agron, Koichi Yamada
  • Publication number: 20180011696
    Abstract: Technologies for binary translation include a computing device that allocates a translation cache shared by all threads associated with a corresponding execution domain. The computing device assigns a thread to an execution domain, translates original binary code of the thread to generate translated binary code, and installs the translated binary code into the corresponding translation cache for execution. The computing device may allocate a global region cache, generate region metadata associated with the original binary code of a thread, and store the region metadata in the global region cache. The original binary code may be translated using the region metadata. The computing device may allocate a global prototype cache, translate the original binary code of a thread to generate prototype code, and install the prototype code in the global prototype cache. The prototype code may be a non-executable version of the translated binary code. Other embodiments are described and claimed.
    Type: Application
    Filed: July 6, 2016
    Publication date: January 11, 2018
    Inventors: Koichi Yamada, Jose A. Baiocchi Paredes, Abhik Sarkar, Ajay Harikumar, Jiwei Lu
  • Publication number: 20170371578
    Abstract: Methods, apparatus, and system to identify a memory contention with respect to a process, re-write the process to form a transactional process, and execute the transactional process in a speculative execution.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 28, 2017
    Inventors: Keqiang WU, Jiwei LU, Koichi YAMADA, Yong-Fong LEE
  • Patent number: 9766911
    Abstract: Aspects of the invention are directed to a systems and methods for operating a non-native binary in dynamic binary translation environment. In accordance with an embodiment, there is provided a computer program product in a computer readable medium. The product includes program code for receiving a non-native binary in a computer readable medium and program code for translating the non-native binary. Additionally, the product includes program code for executing the translated non-native binary, the non-native binary including one or more threads, and program code for pausing execution of the translated non-native binary. The product also includes program code for providing guest instruction boundary information to a monitoring process and program code for analyzing a state of each thread of the translated non-native binary. Moreover, the product includes program code for fast-forwarding at least one thread so that its state is consistent with the guest instruction boundary.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: September 19, 2017
    Assignee: ORACLE AMERICA, INC.
    Inventors: Abhinav Das, Jiwei Lu, William Y. Chen, Chandramouli Banerjee
  • Patent number: 9665374
    Abstract: A method is described. The method includes receiving an instruction, accessing a return cache to load a predicted return target address upon determining that the instruction is a return instruction, searching a lookup table for executable binary code upon determining that the predicted translated return target address is incorrect and executing the executable binary code to perform a binary translation.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: May 30, 2017
    Assignee: Intel Corporation
    Inventors: Koichi Yamada, Ashish Bijlani, Jiwei Lu, Cheng Yan Zhao
  • Publication number: 20160378498
    Abstract: Systems, methods, and apparatuses for last branch record support are described. In an embodiment, a hardware processor core comprises a hardware execution unit to execute a branch instruction, at least two last branch record (LBR) registers to store a source and destination information of a branch taken during program execution, wherein an entry in a LBR register to include an encoding of the branch, a write bit array to indicate which LBR register is architecturally correct, an architectural bit array to indicate when an LBR register has been written, and a plurality of top of stack pointers to indicate which LBR register in a LBR register stack is to be written.
    Type: Application
    Filed: June 27, 2015
    Publication date: December 29, 2016
    Inventors: Paul Caprioli, Koichi Yamada, Jason M. Agron, Jiwei Lu
  • Patent number: 9477453
    Abstract: Technologies for shadow stack management include a computing device that, when executing a translated call routine in a translated binary, pushes a native return address on to a native stack of the computing device, adds a constant offset to a stack pointer of the computing device, executes a native call instruction to a translated call target, and, after executing the native call instruction, subtracts the constant offset from the stack pointer. Executing the native call instruction pushes a translated return address onto a shadow stack of the computing device. The computing device may map two or more virtual memory pages of the shadow stack onto a single physical memory page. The computing device may execute a translated return routine that pops the native return address from the native stack, adds the constant offset to the stack pointer, and executes a native return instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Tugrul Ince, Koichi Yamada, Paul Caprioli, Jiwei Lu
  • Patent number: 9411363
    Abstract: One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: August 9, 2016
    Assignee: Intel Corporation
    Inventors: Keqiang Wu, Jiwei Lu, Yong-Fong Lee
  • Publication number: 20160188372
    Abstract: Technologies for partial binary translation on multi-core platforms include a shared translation cache, a binary translation thread scheduler, a global installation thread, and a local translation thread and analysis thread for each processor core. On detection of a hotspot, the thread scheduler first resumes the global thread if suspended, next activates the global thread if a translation cache operation is pending, and last schedules local translation or analysis threads for execution. Translation cache operations are centralized in the global thread and decoupled from analysis and translation. The thread scheduler may execute in a non-preemptive nucleus, and the translation and analysis threads may execute in a preemptive runtime. The global thread may be primarily preemptive with a small non-preemptive nucleus to commit updates to the shared translation cache. The global thread may migrate to any of the processor cores. Forward progress is guaranteed. Other embodiments are described and claimed.
    Type: Application
    Filed: June 28, 2013
    Publication date: June 30, 2016
    Inventors: Abhik SARKAR, Jiwei LU, Palanivelrajan Rajan SHANMUGAVELAYUTHAM, Jason M. AGRON, Koichi YAMADA
  • Publication number: 20160179547
    Abstract: A method is described. The method includes receiving an instruction, accessing a return cache to load a predicted return target address upon determining that the instruction is a return instruction, searching a lookup table for executable binary code upon determining that the predicted translated return target address is incorrect and executing the executable binary code to perform a binary translation.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Koichi Yamada, Ashish Bijlani, Jiwei Lu, Cheng Yan Zhao
  • Publication number: 20160170438
    Abstract: One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 16, 2016
    Inventors: Keqiang WU, Jiwei Lu, Yong-Fong Lee
  • Patent number: 9146831
    Abstract: A method of reproducing runtime environment for debugging an application is disclosed. The method includes accessing an optimizer file from a non-volatile storage medium. The optimizer file includes a runtime environment, application definition information, and a log. The log includes summaries of a plurality of events, the plurality of actions, and a time mark of occurrence for each of the plurality of actions. A runtime environment for debugging the application is then defined and the application runtime is set up using the application definition information in the optimizer file.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 29, 2015
    Assignee: Oracle America, Inc.
    Inventors: William Y. Chen, Jiwei Lu
  • Publication number: 20150095628
    Abstract: Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for a target address of a branch instruction associated with a translated portion of a routine in a table comprising valid target addresses. Other embodiments are described and claimed.
    Type: Application
    Filed: May 23, 2013
    Publication date: April 2, 2015
    Inventors: Koichi Yamada, Palanivelra Shanmugavelayutham, Arvind Krishnaswamy, Jason M. Agron, Jiwei Lu
  • Patent number: 8953366
    Abstract: The present invention proposes an electronic memory device comprising a memory line including a memory domain. The memory line may contain a number of memory domains and a number of fixed domains, wherein each memory domain stores a single binary bit value. A multiferroic element may be disposed proximate to each memory domain allowing the magnetization of the memory domain to be changed using a spin torque current, and ensuring the stability of the magnetization of the domain when it is not being written. The domain boundary between the memory domain and one of its adjacent fixed domains may thereby be moved. An antiferromagnetic element may be disposed proximate to each fixed domain to ensure the stability of the magnetization of these. The value of each memory domain may be read by applying a voltage to a magnetic tunnel junction comprising the memory domain and measuring the current flowing through it.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: February 10, 2015
    Assignee: University of Virginia Patent Foundation
    Inventors: Stuart A. Wolf, Jiwei Lu, Mircea R. Stan