Patents by Inventor Jiwei Lu

Jiwei Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160170438
    Abstract: One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 16, 2016
    Inventors: Keqiang WU, Jiwei Lu, Yong-Fong Lee
  • Patent number: 9146831
    Abstract: A method of reproducing runtime environment for debugging an application is disclosed. The method includes accessing an optimizer file from a non-volatile storage medium. The optimizer file includes a runtime environment, application definition information, and a log. The log includes summaries of a plurality of events, the plurality of actions, and a time mark of occurrence for each of the plurality of actions. A runtime environment for debugging the application is then defined and the application runtime is set up using the application definition information in the optimizer file.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 29, 2015
    Assignee: Oracle America, Inc.
    Inventors: William Y. Chen, Jiwei Lu
  • Publication number: 20150095628
    Abstract: Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for a target address of a branch instruction associated with a translated portion of a routine in a table comprising valid target addresses. Other embodiments are described and claimed.
    Type: Application
    Filed: May 23, 2013
    Publication date: April 2, 2015
    Inventors: Koichi Yamada, Palanivelra Shanmugavelayutham, Arvind Krishnaswamy, Jason M. Agron, Jiwei Lu
  • Patent number: 8953366
    Abstract: The present invention proposes an electronic memory device comprising a memory line including a memory domain. The memory line may contain a number of memory domains and a number of fixed domains, wherein each memory domain stores a single binary bit value. A multiferroic element may be disposed proximate to each memory domain allowing the magnetization of the memory domain to be changed using a spin torque current, and ensuring the stability of the magnetization of the domain when it is not being written. The domain boundary between the memory domain and one of its adjacent fixed domains may thereby be moved. An antiferromagnetic element may be disposed proximate to each fixed domain to ensure the stability of the magnetization of these. The value of each memory domain may be read by applying a voltage to a magnetic tunnel junction comprising the memory domain and measuring the current flowing through it.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: February 10, 2015
    Assignee: University of Virginia Patent Foundation
    Inventors: Stuart A. Wolf, Jiwei Lu, Mircea R. Stan
  • Publication number: 20140089903
    Abstract: A method of reproducing runtime environment for debugging an application is disclosed. The method includes accessing an optimizer file from a non-volatile storage medium. The optimizer file includes a runtime environment, application definition information, and a log. The log includes summaries of a plurality of events, the plurality of actions, and a time mark of occurrence for each of the plurality of actions. A runtime environment for debugging the application is then defined and the application runtime is set up using the application definition information in the optimizer file.
    Type: Application
    Filed: November 27, 2013
    Publication date: March 27, 2014
    Applicant: Oracle America, Inc.
    Inventors: William Y. Chen, Jiwei Lu
  • Patent number: 8627302
    Abstract: A method of reproducing runtime environment for debugging an application includes reading an optimizer file from a non-volatile storage medium. The optimizer file includes a runtime environment, application definition information, and a log. The log includes summaries of events, actions, and a time mark of occurrence for each of the actions. A runtime environment for debugging the application is then defined and the application runtime is set up using the application definition information in the optimizer file. Further, the method includes running the application, attaching an optimizer, and triggering each of the actions to occur at a time mark of occurrence associated with each of the actions. Then, each of the actions and associated events is analyzed by comparing the events produced by running the application with the events in the optimizer file. If a fault is produced by the triggering, a debugger is invoked to analyze the fault.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: January 7, 2014
    Assignee: Oracle America, Inc.
    Inventors: William Y. Chen, Jiwei Lu
  • Patent number: 8521760
    Abstract: Techniques for selectively translating resource requests from a program running on a computer system are disclosed. The resource request may be a request to access a file, library file, API, etc. The resource request may be a system call or library call. The computer program may be non-native to the computer system. Translation of resource requests may occur within the operating system or outside it. A resource request containing a reference to a first path and file name may be selectively translated by altering the resource request to contain a reference to a second path and file name. After selectively translating a request, he request is caused to be serviced. A resource request may be serviced by forwarding it to an operating system, and a result may be sent back to the program.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: August 27, 2013
    Assignee: Oracle America, Inc.
    Inventors: Abhinav Das, William Y. Chen, Jiwei Lu, Chandramouli Banerjee
  • Patent number: 8473930
    Abstract: A method for executing non-native binaries on a host computer architecture comprises receiving the guest executable binary into a computer readable medium. The guest executable binary is executed on the host computer architecture by translating the guest executable binary into a translated executable binary. Each instruction of the translated executed binary is then executed on the host computer architecture. Signals are responded to by placing signal information on a signal queue and deferring signal handling until a safe point is reached. A computer system implementing the method is also provided.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: June 25, 2013
    Assignee: Oracle America, Inc.
    Inventors: Abhinav Das, Jiwei Lu, William Y. Chen, Chandramouli Banerjee
  • Publication number: 20130058157
    Abstract: The present invention proposes an electronic memory device comprising a memory line including a memory domain. The memory line may contain a number of memory domains and a number of fixed domains, wherein each memory domain stores a single binary bit value. A multiferroic element may be disposed proximate to each memory domain allowing the magnetization of the memory domain to be changed using a spin torque current, and ensuring the stability of the magnetization of the domain when it is not being written. The domain boundary between the memory domain and one of its adjacent fixed domains may thereby be moved. An antiferromagnetic element may be disposed proximate to each fixed domain to ensure the stability of the magnetization of these. The value of each memory domain may be read by applying a voltage to a magnetic tunnel junction comprising the memory domain and measuring the current flowing through it.
    Type: Application
    Filed: May 11, 2011
    Publication date: March 7, 2013
    Applicant: University of Virginia Patent Foundation, d/b/a University of Virginia Licensing & Ventures Group
    Inventors: Stuart A. Wolf, Jiwei Lu, Mircea R. Stan
  • Patent number: 8346531
    Abstract: A method for executing non-native binaries on a host computer architecture comprises receiving a guest executable binary encoded on a computer readable medium. The guest executable binary is executable on a first computer architecture. Moreover, the guest executable binary includes a mutex lock encoded instructions for implementing a mutex lock. The guest executable binary is then executed on the host computer architecture by first translating the guest executable binary to a translated executable binary. The encoded instructions for implementing a mutex lock are translated by mapping the mutex lock to an instance of a compound mutex lock data structure. A computer system implementing methods for executing non-native binaries on a host computer architecture is also provided.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: January 1, 2013
    Assignee: Oracle America, Inc.
    Inventors: Abhinav Das, Jiwei Lu, William Y. Chen, Chandramouli Banerjee
  • Patent number: 8230402
    Abstract: A method for testing and debugging of dynamic binary translation wherein a dynamic binary translator allows a target binary to be executed transparently on a host machine having a different computer architecture than the target machine involves selecting a minimum set of target machine states for simulation at run-time. A series of target machine instructions from the target binary is translated into a series of host machine instructions. During translation, a plurality of check points are inserted into the series of host machine instructions. During translation, a plurality of verification points are inserted into the series of host machine instructions. The series of host machine instructions, including the check points and verification points, are executed. Execution of a check point determines a simulated target machine state. Execution of a verification point sends information pertaining to simulated target machine states to an external verifier.
    Type: Grant
    Filed: September 30, 2007
    Date of Patent: July 24, 2012
    Assignee: Oracle America, Inc.
    Inventors: William Y. Chen, Jiwei Lu, Geetha K. Vallabhaneni
  • Patent number: 8020155
    Abstract: A mechanism is provided for managing the referencing of at least two versions of a function. A first version is a single threaded version that does not ensure multi-thread safety. A second version is a multi threaded version that does ensure multi-thread safety. The mechanism determines whether a set of executable code (e.g. a program) is currently executing in single-threaded mode or multi-threaded mode. If the executable code is executing in single-threaded mode, then the mechanism causes the executable code to reference the first version of the function. If the executable code is executing in multi-threaded mode, then the mechanism causes the executable code to reference the second version of the function. By doing so, the mechanism ensures that the additional overhead of ensuring multi-thread safety is incurred only when it is needed. In this manner, the mechanism makes execution of the function more optimal.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: September 13, 2011
    Assignee: Oracle America, Inc.
    Inventors: Jiwei Lu, William Yu-Wei Chen
  • Publication number: 20100274551
    Abstract: Aspects of the invention are directed to a systems and methods for operating a non-native binary in dynamic binary translation environment. In accordance with an embodiment, there is provided a computer program product in a computer readable medium. The product includes program code for receiving a non-native binary in a computer readable medium and program code for translating the non-native binary. Additionally, the product includes program code for executing the translated non-native binary, the non-native binary including one or more threads, and program code for pausing execution of the translated non-native binary. The product also includes program code for providing guest instruction boundary information to a monitoring process and program code for analyzing a state of each thread of the translated non-native binary.
    Type: Application
    Filed: April 24, 2009
    Publication date: October 28, 2010
    Applicant: Sun Microsystems, Inc.
    Inventors: Abhinav Das, Jiwei Lu, William Y. Chen, Chandramouli Banerjee
  • Publication number: 20100169308
    Abstract: Techniques for selectively translating resource requests from a program running on a computer system are disclosed. The resource request may be a request to access a file, library file, API, etc. The resource request may be a system call or library call. The computer program may be non-native to the computer system. Translation of resource requests may occur within the operating system or outside it. A resource request containing a reference to a first path and file name may be selectively translated by altering the resource request to contain a reference to a second path and file name. After selectively translating a request, he request is caused to be serviced. A resource request may be serviced by forwarding it to an operating system, and a result may be sent back to the program.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Inventors: Abhinav Das, William Y. Chen, Jiwei Lu, Chandramouli Banerjee
  • Publication number: 20100114555
    Abstract: A method for executing non-native binaries on a host computer architecture comprises receiving a guest executable binary encoded on a computer readable medium. The guest executable binary is executable on a first computer architecture. Moreover, the guest executable binary includes a mutex lock encoded instructions for implementing a mutex lock. The guest executable binary is then executed on the host computer architecture by first translating the guest executable binary to a translated executable binary. The encoded instructions for implementing a mutex lock are translated by mapping the mutex lock to an instance of a compound mutex lock data structure. A computer system implementing methods for executing non-native binaries on a host computer architecture is also provided.
    Type: Application
    Filed: November 5, 2008
    Publication date: May 6, 2010
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Abhinav Das, Jiwei Lu, William Y. Chen, Chandramouli Banerjee
  • Publication number: 20100115497
    Abstract: A method for executing non-native binaries on a host computer architecture comprises receiving the guest executable binary into a computer readable medium. The guest executable binary is executed on the host computer architecture by translating the guest executable binary into a translated executable binary. Each instruction of the translated executed binary is then executed on the host computer architecture. Signals are responded to by placing signal information on a signal queue and deferring signal handling until a safe point is reached. A computer system implementing the method is also provided.
    Type: Application
    Filed: November 5, 2008
    Publication date: May 6, 2010
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Abhinav Das, Jiwei Lu, William Y. Chen, Chandramouli Banerjee
  • Publication number: 20090138859
    Abstract: A method of reproducing runtime environment for debugging an application is disclosed. The method includes reading an optimizer file from a non-volatile storage medium. The optimizer file includes a runtime environment, application definition information, and a log. The log includes summaries of a plurality of events, the plurality of actions, and a time mark of occurrence for each of the plurality of actions. A runtime environment for debugging the application is then defined and the application runtime is set up using the application definition information in the optimizer file.
    Type: Application
    Filed: November 27, 2007
    Publication date: May 28, 2009
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: William Y. Chen, Jiwei Lu
  • Publication number: 20090089758
    Abstract: A method for testing and debugging of dynamic binary translation wherein a dynamic binary translator allows a target binary to be executed transparently on a host machine having a different computer architecture than the target machine involves selecting a minimum set of target machine states for simulation at run-time. A series of target machine instructions from the target binary is translated into a series of host machine instructions. During translation, a plurality of check points are inserted into the series of host machine instructions. During translation, a plurality of verification points are inserted into the series of host machine instructions. The series of host machine instructions, including the check points and verification points, are executed. Execution of a check point determines a simulated target machine state. Execution of a verification point sends information pertaining to simulated target machine states to an external verifier.
    Type: Application
    Filed: September 30, 2007
    Publication date: April 2, 2009
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: William Y. Chen, Jiwei Lu, Geetha K. Vallabhaneni
  • Publication number: 20080127071
    Abstract: A mechanism is provided for managing the referencing of at least two versions of a function. A first version is a single threaded version that does not ensure multi-thread safety. A second version is a multi threaded version that does ensure multi-thread safety. The mechanism determines whether a set of executable code (e.g. a program) is currently executing in single-threaded mode or multi-threaded mode. If the executable code is executing in single-threaded mode, then the mechanism causes the executable code to reference the first version of the function. If the executable code is executing in multi-threaded mode, then the mechanism causes the executable code to reference the second version of the function. By doing so, the mechanism ensures that the additional overhead of ensuring multi-thread safety is incurred only when it is needed. In this manner, the mechanism makes execution of the function more optimal.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 29, 2008
    Inventors: Jiwei Lu, William Yu-Wei Chen