Patents by Inventor Jixin Yu

Jixin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220352091
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory opening fill structures including a respective vertical semiconductor channel and a respective memory film, and support pillar structures including a respective dummy vertical semiconductor channel, a respective dummy memory film, and a vertical stack of dielectric spacer fins located at levels of the electrically conductive layers and interposed between the electrically conductive layers and the respective dummy memory film.
    Type: Application
    Filed: August 31, 2021
    Publication date: November 3, 2022
    Inventors: Jixin YU, Johann ALSMEIER, Koichi MATSUNO
  • Patent number: 11380707
    Abstract: A three-dimensional memory device includes layer stacks located over a substrate and laterally spaced apart from each other by backside trenches. Each of the layer stacks includes a respective alternating stack of insulating layers and electrically conductive layers. Memory openings vertically extend through a respective one of the alternating stacks and are filled with a respective memory opening fill structure. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements. Each backside trench fill structure includes a respective row of backside trench bridge structures that are more distal from the substrate than a most distal one of the electrically conductive layers is from the substrate. The backside trench bridge structures can provide structural support during a replacement process that forms the electrically conductive layers.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: July 5, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Koichi Matsuno, Jixin Yu, Johann Alsmeier
  • Publication number: 20220181348
    Abstract: A three-dimensional memory device includes layer stacks located over a substrate and laterally spaced apart from each other by backside trenches. Each of the layer stacks includes a respective alternating stack of insulating layers and electrically conductive layers. Memory openings vertically extend through a respective one of the alternating stacks and are filled with a respective memory opening fill structure. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements. Each backside trench fill structure includes a respective row of backside trench bridge structures that are more distal from the substrate than a most distal one of the electrically conductive layers is from the substrate. The backside trench bridge structures can provide structural support during a replacement process that forms the electrically conductive layers.
    Type: Application
    Filed: December 9, 2020
    Publication date: June 9, 2022
    Inventors: Koichi MATSUNO, Jixin YU, Johann ALSMEIER
  • Publication number: 20210210503
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a vertical stack of memory elements, a dielectric moat structure vertically extending through the alternating stack and including an annular dielectric plate portion at each level of the electrically conductive layers that laterally surrounds a respective dielectric material plate, and an interconnection via structure laterally surrounded by the dielectric moat structure and vertically extending through each insulating layer within the alternating stack.
    Type: Application
    Filed: November 30, 2020
    Publication date: July 8, 2021
    Inventors: Koichi MATSUNO, James KAI, Jixin YU, Johann ALSMEIER, Yoshitaka OTSU
  • Patent number: 11043455
    Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. The vertically alternating sequence is divided into alternating stacks of insulating layers and sacrificial material layers by forming backside trenches therethrough. Each neighboring pair of alternating stacks is laterally spaced apart from each other by a respective backside trench. The sacrificial material layers are replaced with multipart layers.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: June 22, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Johann Alsmeier, Jixin Yu
  • Publication number: 20210028111
    Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. The vertically alternating sequence is divided into alternating stacks of insulating layers and sacrificial material layers by forming backside trenches therethrough. Each neighboring pair of alternating stacks is laterally spaced apart from each other by a respective backside trench. The sacrificial material layers are replaced with multipart layers.
    Type: Application
    Filed: July 23, 2019
    Publication date: January 28, 2021
    Inventors: James KAI, Johann Alsmeier, Jixin YU
  • Patent number: 10854629
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A staircase region having stepped surfaces is formed by patterning the alternating stack. Memory opening fill structures are formed in a memory array region, and support pillar structures are formed in the staircase region. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. The support pillar structures include first support pillar structures and having a first maximum lateral dimension and second support pillar structures having a second maximum lateral dimension that is less than the first maximum lateral dimension and interlaced with the first support pillar structures. The sacrificial material layers are replaced with electrically conductive layers.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: December 1, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chun Ge, Jixin Yu, Fabo Yu, Xin Yuan Li, Yanli Zhang
  • Patent number: 10825826
    Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: November 3, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Tae-Kyung Kim, Johann Alsmeier, Yan Li, Jian Chen
  • Patent number: 10804197
    Abstract: A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers located over a semiconductor region, and laterally spaced from each other by a backside trench, memory stack structures extending through the pair of alternating, each memory stack structure containing a vertical semiconductor channel and a memory film, and a backside contact assembly located in the backside trench. The backside contact assembly includes an isolation dielectric spacer contacting the pair of alternating stacks, a conductive liner contacting inner sidewalls of the isolation dielectric spacer and a top surface of the semiconductor region, and composite non-metallic core containing at least one outer dielectric fill material portion that is laterally enclosed by a lower portion of the conductive liner and a dielectric core contacting an inner sidewall of the at least one outer dielectric fill material portion.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: October 13, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Motoki Kawasaki, Arata Okuyama, Xun Gu, Kengo Kajiwara, Jixin Yu
  • Publication number: 20200312865
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A staircase region having stepped surfaces is formed by patterning the alternating stack. Memory opening fill structures are formed in a memory array region, and support pillar structures are formed in the staircase region. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. The support pillar structures include first support pillar structures and having a first maximum lateral dimension and second support pillar structures having a second maximum lateral dimension that is less than the first maximum lateral dimension and interlaced with the first support pillar structures. The sacrificial material layers are replaced with electrically conductive layers.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Chun Ge, Jixin Yu, Fabo Yu, Xin Yuan Li, Yanli Zhang
  • Publication number: 20200312765
    Abstract: A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers located over a semiconductor region, and laterally spaced from each other by a backside trench, memory stack structures extending through the pair of alternating, each memory stack structure containing a vertical semiconductor channel and a memory film, and a backside contact assembly located in the backside trench. The backside contact assembly includes an isolation dielectric spacer contacting the pair of alternating stacks, a conductive liner contacting inner sidewalls of the isolation dielectric spacer and a top surface of the semiconductor region, and composite non-metallic core containing at least one outer dielectric fill material portion that is laterally enclosed by a lower portion of the conductive liner and a dielectric core contacting an inner sidewall of the at least one outer dielectric fill material portion.
    Type: Application
    Filed: July 19, 2019
    Publication date: October 1, 2020
    Inventors: Motoki KAWASAKI, Arata OKUYAMA, Xun GU, Kengo KAJIWARA, Jixin YU
  • Publication number: 20200295029
    Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Jixin Yu, Tae-Kyung Kim, Johann Alsmeier, Yan Li, Jian Chen
  • Patent number: 10707228
    Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: July 7, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Tae-Kyung Kim, Johann Alsmeier, Yan Li, Jian Chen
  • Patent number: 10672657
    Abstract: A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matthew Park, Adam L. Olson, Jixin Yu
  • Patent number: 10658381
    Abstract: Memory dies on a wafer may include multiple memory blocks including bit lines extending along different directions. A memory die may include a first-type plane including first memory blocks and a second-type plane including second memory blocks. In this case, memory blocks having different bit line directions may be formed within a same memory die. An exposure field may include multiple types of memory dies that are oriented in different orientations. The bit line directions may be oriented differently in the multiple types of memory dies. Each lithographic exposure process may include a first step in which lithographic patterns in first exposure fields are oriented in one direction, and a second step in which lithographic patterns in second exposure fields are oriented in another direction. The different orientations of bit lines and word lines may change local directions of stress to reduce wafer distortion.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: May 19, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Fumiaki Toyama, Masaaki Higashitani, Tong Zhang, Chun Ge, Xin Yuan Li, Johann Alsmeier
  • Publication number: 20200066745
    Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.
    Type: Application
    Filed: February 25, 2019
    Publication date: February 27, 2020
    Inventors: Jixin Yu, Tae-Kyung Kim, Johann Alsmeier, Yan Li, Jian Chen
  • Patent number: 10453748
    Abstract: A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Matthew Park, Adam L. Olson, Jixin Yu
  • Patent number: 10381443
    Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Hiroyuki Ogawa, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
  • Patent number: 10354956
    Abstract: A contact level silicon oxide layer and a silicon nitride layer is formed over a semiconductor device on a semiconductor substrate. A contact via cavity extending to the semiconductor device is formed. A lower contact via structure portion is formed and recessed between top and bottom surface of the silicon nitride layer. An upper contact via structure portion including a hydrogen diffusion barrier material is formed in a remaining volume of the contact via cavity to provide a contact via structure. A three-dimensional memory array is formed over the silicon nitride layer. Metal interconnect structures are formed to provide electrical connection between the contact via structure and a node of the three-dimensional memory array. The hydrogen diffusion barrier material and the silicon nitride layer block downward diffusion of hydrogen.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 16, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Daxin Mao, Hiroyuki Ogawa, Johann Alsmeier
  • Publication number: 20190214344
    Abstract: A contact level silicon oxide layer and a silicon nitride layer is formed over a semiconductor device on a semiconductor substrate. A contact via cavity extending to the semiconductor device is formed. A lower contact via structure portion is formed and recessed between top and bottom surface of the silicon nitride layer. An upper contact via structure portion including a hydrogen diffusion barrier material is formed in a remaining volume of the contact via cavity to provide a contact via structure. A three-dimensional memory array is formed over the silicon nitride layer. Metal interconnect structures are formed to provide electrical connection between the contact via structure and a node of the three-dimensional memory array. The hydrogen diffusion barrier material and the silicon nitride layer block downward diffusion of hydrogen.
    Type: Application
    Filed: January 5, 2018
    Publication date: July 11, 2019
    Inventors: Jixin Yu, Daxin Mao, Hiroyuki Ogawa, Johann Alsmeier