Abstract: Apparatus and techniques for an integrated circuit (IC) package to automatically detect, through an input/out pin, external component parameters and parasitics. An example IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin, and configured to detect at least one of a resistance, an inductance, or a capacitance, respectively, of a lumped parameter model for the component external to the IC package. The resistance detector, inductance detector, or capacitance detector may also be configured to detect parasitics associated with at least one of the component, the pin, or a connection between the component and the pin.

Abstract: Apparatus and techniques for an integrated circuit (IC) package to automatically detect, through an input/out pin, external component parameters and parasitics. An example IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin, and configured to detect at least one of a resistance, an inductance, or a capacitance, respectively, of a lumped parameter model for the component external to the IC package. The resistance detector, inductance detector, or capacitance detector may also be configured to detect parasitics associated with at least one of the component, the pin, or a connection between the component and the pin.

Abstract: The disclosure relates to an apparatus including: a first set of one or more field effect transistors (FETs) coupled between a first voltage rail and a load; a second set of one or more FETs coupled between the first voltage rail and the load; a gate voltage control circuit configured to: provide a first set of gate voltages to first and second gates of the first and second sets of one or more FETs in accordance with a first mode of operation, respectively; and provide a second set of gate voltages to the first and second gates of the first and second sets of one or more FETs in accordance with a second mode of operation, respectively; and a voltage droop compensation circuit configured to control an output voltage across the load during a transition from the first mode of operation to the second mode of operation.

Abstract: In certain aspects, a system includes an amplifying circuit having an input and an output, a high-pass filter coupled between a gate of a pass transistor of a low dropout (LDO) regulator and the input of the amplifying circuit, and a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the gate of the pass transistor.

Abstract: In certain aspects, a system includes an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to a gate of a pass transistor of a low dropout (LDO) regulator. The system also includes a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the input of the amplifying circuit.

Abstract: A power supply circuit and techniques for voltage regulation are described. Certain aspects provide a method of supplying power by a power supply circuit. The method generally includes: generating an output voltage based on a voltage at a Vin node via a first transistor having a gate coupled to a gate of a second transistor, wherein a source of the second transistor is coupled to the Vin node and wherein a drain of the second transistor is coupled a drain of a third transistor; and sourcing a current to the third transistor, wherein during a light load condition of the power supply circuit, the current varies based on the voltage at a Vout node of the power supply circuit, and during a heavy load condition of the power supply circuit, the current is limited based on a current threshold.

Abstract: The disclosure relates to an apparatus including: a first set of one or more field effect transistors (FETs) coupled between a first voltage rail and a load; a second set of one or more FETs coupled between the first voltage rail and the load; a gate voltage control circuit configured to: provide a first set of gate voltages to first and second gates of the first and second sets of one or more FETs in accordance with a first mode of operation, respectively; and provide a second set of gate voltages to the first and second gates of the first and second sets of one or more FETs in accordance with a second mode of operation, respectively; and a voltage droop compensation circuit configured to control an output voltage across the load during a transition from the first mode of operation to the second mode of operation.

Abstract: Certain aspects of the present disclosure provide a circuit for clock signal generation. The circuit generally includes a plurality of clock generation circuits configured to generate a plurality of clock signals from a clock signal, and a power supply circuit having an output coupled to power supply inputs of the plurality of clock generation circuits. The circuit may also include a capacitor array coupled to the output of the power supply circuit and include a plurality of capacitive elements, the capacitor array being configured to selectively couple each of the plurality of capacitive elements to the output of the power supply circuit based on a quantity of one or more active clock generation circuits of the plurality of clock generation circuits.

Abstract: In certain aspects, a system includes an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to a gate of a pass transistor of a low dropout (LDO) regulator. The system also includes a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the input of the amplifying circuit.

Abstract: Aspects of the present disclosure provide a voltage reference architecture. An example circuit generally includes a resistor ladder, a reference current source, and a plurality of multiplexers. The resistor ladder comprises a plurality of resistive elements coupled in series. The reference current source has an output coupled to the resistor ladder. The plurality of multiplexers have inputs coupled to one or more nodes between the plurality of resistive elements and the output of the reference current source, each of the multiplexers having an output selectively coupled to one of the inputs of the multiplexer.

Abstract: Aspects of the present disclosure provide a voltage reference architecture. An example circuit generally includes a resistor ladder, a reference current source, and a plurality of multiplexers. The resistor ladder comprises a plurality of resistive elements coupled in series. The reference current source has an output coupled to the resistor ladder. The plurality of multiplexers have inputs coupled to one or more nodes between the plurality of resistive elements and the output of the reference current source, each of the multiplexers having an output selectively coupled to one of the inputs of the multiplexer.

Abstract: According to certain aspects, a driver includes an output transistor coupled between a first rail and an output of the driver, a first current source coupled to a gate of the output transistor, a second current source, and a switch, wherein the switch and the second current source are coupled in series between the gate of the output transistor and a second rail. The driver also includes a current sensor configured to generate a sense current based on an output current of the driver, and a reference current source configured to generate a reference current, wherein the current sensor and the reference current source are coupled to a control input of the switch.

Abstract: According to certain aspects, a driver includes an output transistor coupled between a first rail and an output of the driver, a first current source coupled to a gate of the output transistor, a second current source, and a switch, wherein the switch and the second current source are coupled in series between the gate of the output transistor and a second rail. The driver also includes a current sensor configured to generate a sense current based on an output current of the driver, and a reference current source configured to generate a reference current, wherein the current sensor and the reference current source are coupled to a control input of the switch.

Abstract: According to certain aspects, a driver includes an output transistor coupled between a first rail and an output of the driver, a first current source coupled to a gate of the output transistor, a second current source, and a switch, wherein the switch and the second current source are coupled in series between the gate of the output transistor and a second rail. The driver also includes a current sensor configured to generate a sense current based on an output current of the driver, and a reference current source configured to generate a reference current, wherein the current sensor and the reference current source are coupled to a control input of the switch.

Abstract: An electronic circuit for single-event latch-up (SEL) detection and protection of a target integrated circuit (IC) is disclosed. The circuit comprises: a first detector configured for detecting an absolute load current (i) and comparing the absolute load current (i) with a threshold current (ith); a second detector configured for detecting a rate of change of load current (di/dt) and comparing the rate of change of load current (di/dt) with a threshold current change rate (di/dt)th; and a determination module for triggering a power shut-down to the target IC if the absolute load current (i) exceeds the threshold current (ith) and/or the rate of change of load current (di/dt) exceeds the threshold current change rate (di/dt)th.

Abstract: A method for providing a voltage reference at a present operating temperature in a circuit is provided. The circuit comprises a first MOS transistor having a first threshold voltage; and a second MOS transistor having a second threshold voltage different from the first threshold voltage is provided. Temperature insensitivity is obtained by compensating the difference between the first threshold voltage and the second threshold voltage with a parameter representative of the present operating temperature.

Abstract: An electronic circuit for single-event latch-up (SEL) detection and protection of a target integrated circuit (IC) is disclosed. The circuit comprises: a first detector configured for detecting an absolute load current (i) and comparing the absolute load current (i) with a threshold current (ith); a second detector configured for detecting a rate of change of load current (di/dt) and comparing the rate of change of load current (di/dt) with a threshold current change rate (di/dt)th; and a determination module for triggering a power shut-down to the target IC if the absolute load current (i) exceeds the threshold current (ith) and/or the rate of change of load current (di/dt) exceeds the threshold current change rate (di/dt)th.

Abstract: A method for providing a voltage reference at a present operating temperature in a circuit is provided. The circuit comprises a first MOS transistor having a first threshold voltage; and a second MOS transistor having a second threshold voltage different from the first threshold voltage is provided.