Patents by Inventor Jo Fei Wang

Jo Fei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10113233
    Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo Fei Wang, Ming-Yu Fan, Jong-I Mou
  • Patent number: 10047439
    Abstract: A method and system for removing control action effects from inline measurement data for tool condition monitoring is disclosed. An exemplary method includes determining a control action effect that contributes to an inline measurement, wherein the inline measurement indicates a wafer characteristic of a wafer processed by a process tool; and evaluating the inline measurement without the control action effect contribution to determine a condition of the process tool.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Feng Tsai, Chia-Tong Ho, Sunny Wu, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
  • Patent number: 9870896
    Abstract: A system, a method, and a non-transitory computer readable storage medium for controlling an ion implanter are disclosed herein. The system includes a sample module and a control module. The sample module is configured to generate a summarized value from process data of the ion implanter, and the process data correspond to a control parameter. The control module is configured to tune a control parameter, and the control module performs an ion implantation by releasing tools of the ion implanter in accordance with the control parameter when the summarized value meets a predetermined stability requirement.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Feng Tsai, Chia-Tong Ho, Chia-Hsing Liao, Sheng-Wei Lee, Jo-Fei Wang, Jong-I Mou
  • Patent number: 9727049
    Abstract: The present disclosure provides various methods for tool condition monitoring, including systems for implementing such monitoring. An exemplary method includes receiving data associated with a process performed on wafers by an integrated circuit manufacturing process tool; and monitoring a condition of the integrated circuit manufacturing process tool using the data. The monitoring includes evaluating the data based on an abnormality identification criterion, an abnormality filtering criterion, and an abnormality threshold to determine whether the data meets an alarm threshold. The method may further include issuing an alarm when the data meets the alarm threshold.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Tong Ho, Po-Feng Tsai, Jung-Chang Chen, Tze-Liang Lee, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
  • Patent number: 9698065
    Abstract: An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer processing chamber. The apparatus further includes radiant heating elements disposed in different zones and operable to heat different portions of a wafer located within the wafer processing chamber. The apparatus further includes sensors disposed outside the wafer processing chamber and operable to monitor energy from the radiant heating elements disposed in the different zones. The apparatus further includes a computer configured to utilize the sensors to characterize the radiant heating elements disposed in the different zones and to provide a calibration for the radiant heating elements disposed in the different zones such that a substantially uniform temperature profile is maintained across a surface of the wafer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tien Chang, Sunny Wu, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
  • Publication number: 20170022611
    Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.
    Type: Application
    Filed: April 7, 2015
    Publication date: January 26, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Lin CHANG, Hsin-Hsien WU, Zin-Chang WEI, Chi-Ming YANG, Chyi Shyuan CHERN, Jun-Lin YEH, Jih-Jse LIN, Jo Fei WANG, Ming-Yu FAN, Jong-I MOU
  • Patent number: 9519285
    Abstract: The present disclosure provides various methods for tuning process parameters of a process tool, including systems for implementing such tuning. An exemplary method for tuning process parameters of a process tool such that the wafers processed by the process tool exhibit desired process monitor items includes defining behavior constraint criteria and sensitivity adjustment criteria; generating a set of possible tool tuning process parameter combinations using process monitor item data associated with wafers processed by the process tool, sensitivity data associated with a sensitivity of the process monitor items to each process parameter, the behavior constraint criteria, and the sensitivity adjustment criteria; generating a set of optimal tool tuning process parameter combinations from the set of possible tool tuning process parameter combinations; and configuring the process tool according to one of the optimal tool tuning process parameter combinations.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: December 13, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Feng Tsai, Chia-Tong Ho, Sunny Wu, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
  • Patent number: 9349660
    Abstract: A system and method for monitoring a process tool of an integrated circuit manufacturing system are disclosed. An exemplary method includes defining zones of an integrated circuit manufacturing process tool; grouping parameters of the integrated circuit manufacturing process tool based on the defined zones; and evaluating a condition of the integrated circuit manufacturing process tool based on the grouped parameters.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Feng Tsai, Chia-Tong Ho, Sunny Wu, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
  • Patent number: 9250619
    Abstract: A system and method of automatically calculating boundaries for a semiconductor fabrication process. The method includes selecting a first parameter for monitoring during a semiconductor fabrication process. A first set of values for the first parameter are received and a group value of the first set is determined. Each value in the first set of values is normalized. A first weighting factor is selected based on a number of values in the first set. The embodiment also includes generating a first and a second boundary value as a function of the weighting factor, the first set normalized values and the group value of the first set and applying the first and second boundary values to control the semiconductor fabrication process.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Hsu, Mei-Jen Wu, Yen-Di Tsen, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
  • Publication number: 20160027708
    Abstract: An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer processing chamber. The apparatus further includes radiant heating elements disposed in different zones and operable to heat different portions of a wafer located within the wafer processing chamber. The apparatus further includes sensors disposed outside the wafer processing chamber and operable to monitor energy from the radiant heating elements disposed in the different zones. The apparatus further includes a computer configured to utilize the sensors to characterize the radiant heating elements disposed in the different zones and to provide a calibration for the radiant heating elements disposed in the different zones such that a substantially uniform temperature profile is maintained across a surface of the wafer.
    Type: Application
    Filed: October 2, 2015
    Publication date: January 28, 2016
    Inventors: Chih-Tien Chang, Sunny Wu, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
  • Patent number: 9158301
    Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sunny Wu, Yen-Di Tsen, Chun-Hsien Lin, Keung Hui, Jo Fei Wang, Jong-I Mou
  • Patent number: 9159597
    Abstract: An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer processing chamber. The apparatus further includes radiant heating elements disposed in different zones and operable to heat different portions of a wafer located within the wafer processing chamber. The apparatus further includes sensors disposed outside the wafer processing chamber and operable to monitor energy from the radiant heating elements disposed in the different zones. The apparatus further includes a computer configured to utilize the sensors to characterize the radiant heating elements disposed in the different zones and to provide a calibration for the radiant heating elements disposed in the different zones such that a substantially uniform temperature profile is maintained across a surface of the wafer.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tien Chang, Sunny Wu, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
  • Patent number: 9141097
    Abstract: A method of automatically determining process parameters for processing equipment includes processing at least one first substrate in the processing equipment at a first time; and processing at least one second substrate in the processing equipment at a second time. The method includes collecting data on process monitors for the at least one first substrate; and the at least one second substrate. The method includes receiving the data by a multiple-input-multiple-output (MIMO) optimization system. The method includes revising a sensitivity matrix, by a MIMO optimizer, using the data and an adaptive-learning algorithm, wherein the adaptive-learning algorithm revises the sensitivity matrix based on a learning parameter which is related to a rate of change of the processing equipment over time. The method includes determining a set of process parameters for the processing equipment by the MIMO optimizer, wherein the MIMO optimizer uses the revised sensitivity matrix to determine the process parameters.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: September 22, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Feng Tsai, Chia-Tong Ho, Sunny Wu, Jo Fei Wang, Jong-I Mou
  • Publication number: 20150211122
    Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.
    Type: Application
    Filed: April 7, 2015
    Publication date: July 30, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Lin CHANG, Hsin-Hsien WU, Zin-Chang WEI, Chi-Ming YANG, Chyi Shyuan CHERN, Jun-Lin YEH, Jih-Jse LIN, Jo Fei WANG, Ming-Yu FAN, Jong-I MOU
  • Publication number: 20150162166
    Abstract: A system, a method, and a non-transitory computer readable storage medium for controlling an ion implanter are disclosed herein. The system includes a sample module and a control module. The sample module is configured to generate a summarized value from process data of the ion implanter, and the process data correspond to a control parameter. The control module is configured to tune a control parameter, and the control module performs an ion implantation by releasing tools of the ion implanter in accordance with the control parameter when the summarized value meets a predetermined stability requirement.
    Type: Application
    Filed: December 6, 2013
    Publication date: June 11, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Feng TSAI, Chia-Tong HO, Chia-Hsing LlAO, Sheng-Wei LEE, Jo-Fei WANG, Jong-I MOU
  • Patent number: 9023664
    Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi-Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo-Fei Wang, Ming-Yu Fan, Jong-I Mou
  • Patent number: 9026239
    Abstract: A method of extending advanced process control (APC) models includes constructing an APC model table including APC model parameters of a plurality of products and a plurality of work stations. The APC model table includes empty cells and cells filled with existing APC model parameters. Average APC model parameters of the existing APC model parameters are calculated, and filled into the empty cells as initial values. An iterative calculation is performed to update the empty cells with updated values.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Feng Tsai, Yen-Di Tsen, Jo Fei Wang, Jong-I Mou
  • Publication number: 20140303765
    Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.
    Type: Application
    Filed: June 19, 2014
    Publication date: October 9, 2014
    Inventors: Sunny Wu, Yen-Di Tsen, Chun-Hsien Lin, Keung Hui, Jo Fei Wang, Jong-I Mou
  • Publication number: 20140207271
    Abstract: The present disclosure provides various methods for tuning process parameters of a process tool, including systems for implementing such tuning. An exemplary method for tuning process parameters of a process tool such that the wafers processed by the process tool exhibit desired process monitor items includes defining behavior constraint criteria and sensitivity adjustment criteria; generating a set of possible tool tuning process parameter combinations using process monitor item data associated with wafers processed by the process tool, sensitivity data associated with a sensitivity of the process monitor items to each process parameter, the behavior constraint criteria, and the sensitivity adjustment criteria; generating a set of optimal tool tuning process parameter combinations from the set of possible tool tuning process parameter combinations; and configuring the process tool according to one of the optimal tool tuning process parameter combinations.
    Type: Application
    Filed: January 23, 2013
    Publication date: July 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Feng Tsai, Chia-Tong Ho, Sunny Wu, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
  • Patent number: 8781614
    Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sunny Wu, Yen-Di Tsen, Chun-Hsien Lin, Keung Hui, Jo Fei Wang, Jong-I Mou