Abstract: A coding efficiency improvement is achieved by performing bit-plane coding in a manner so that coefficient groups for which the set of coded bit-planes is predictively signaled in the datastream, are grouped in two group sets and if a signal is spent in the datastream which signals, for a group set, whether the set of coded bit-planes of all coefficient groups of the respective group set are empty, i.e. all coefficients within the respective group sets are insignificant. In accordance with another aspect, a coding efficiency improvement is achieved by providing bit-plane coding with group-set-wise insignificant signalization according to the first aspect as a coding option alternative relative to the signalization for group sets for which it is signaled that there is no coded prediction residual for the coded bit-planes for the claim groups within the respective group set.

Abstract: A coding efficiency improvement is achieved by performing bit-plane coding in a manner so that coefficient groups for which the set of coded bit-planes is predictively signaled in the datastream, are grouped in two group sets and if a signal is spent in the datastream which signals, for a group set, whether the set of coded bit-planes of all coefficient groups of the respective group set are empty, i.e. all coefficients within the respective group sets are insignificant. In accordance with another aspect, a coding efficiency improvement is achieved by providing bit-plane coding with group-set-wise insignificant signalization according to the first aspect as a coding option alternative relative to the signalization for group sets for which it is signaled that there is no coded prediction residual for the coded bit-planes for the claim groups within the respective group set.

Abstract: An apparatus comprises a first interface for receiving a plurality of partially overlapping images of an object from a corresponding plurality of cameras being arranged along a first and a second direction according to a camera pattern. The apparatus comprises an analyzing unit configured for selecting at least one corresponding reference point in an overlap area of a set of images, and for determining displacement information along the first and the second direction of the reference point in each of the other images of the set of images. A misalignment of the plurality of images along the first and the second direction is compensated by the displacement information so as to obtain aligned images. The apparatus comprises a determining unit configured for determining offset information between principal points of the plurality of cameras using at least three aligned images.

Abstract: A coding efficiency improvement is achieved by performing bit-plane coding in a manner so that coefficient groups for which the set of coded bit-planes is predictively signaled in the datastream, are grouped in two group sets and if a signal is spent in the datastream which signals, for a group set, whether the set of coded bit-planes of all coefficient groups of the respective group set are empty, i.e. all coefficients within the respective group sets are insignificant. In accordance with another aspect, a coding efficiency improvement is achieved by providing bit-plane coding with group-set-wise insignificant signalization according to the first aspect as a coding option alternative relative to the signalization for group sets for which it is signaled that there is no coded prediction residual for the coded bit-planes for the claim groups within the respective group set.

Abstract: The invention relates to a raw image encoder for encoding a raw image of a predetermined color pattern according to which the raw image is partitioned into pixel cell blocks, each pixel cell block comprising four pixels, each pixel being associated with one of three base colors so that each pixel cell block comprises, for each of the three base colors, at least one pixel, the raw image encoder configured to subject the raw image to a color transformation to obtain a color image, by mapping, for each pixel cell block, the four pixels of the pixel cell block onto a color component quadruple forming a sample of the color image, the color component quadruple comprising three color component values of a target color space, and one pseudo color component value, and subject the color image to a multi-component picture encoding to obtain a compressed data stream.

Abstract: The invention relates to an integrated circuit comprising: a row of sink cells, a first driver cell, a second driver cell, an interconnect line connecting the first driver cell to the sink cells of the row; and a shunt line connecting the second driver cell to a point between ends of the interconnect line, wherein a segment of the interconnect line between the point and the first driver cell is bigger than 60% of a length the interconnect line and less than 80% of the length of the interconnect line.

Abstract: An apparatus comprises a first interface for receiving a plurality of partially overlapping images of an object from a corresponding plurality of cameras being arranged along a first and a second direction according to a camera pattern. The apparatus comprises an analyzing unit configured for selecting at least one corresponding reference point in an overlap area of a set of images, and for determining displacement information along the first and the second direction of the reference point in each of the other images of the set of images. A misalignment of the plurality of images along the first and the second direction is compensated by the displacement information so as to obtain aligned images. The apparatus comprises a determining unit configured for determining offset information between principal points of the plurality of cameras using at least three aligned images.

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Abstract: The invention relates to a raw image encoder for encoding a raw image of a predetermined color pattern according to which the raw image is partitioned into pixel cell blocks, each pixel cell block comprising four pixels, each pixel being associated with one of three base colors so that each pixel cell block comprises, for each of the three base colors, at least one pixel, the raw image encoder configured to subject the raw image to a color transformation to obtain a color image, by mapping, for each pixel cell block, the four pixels of the pixel cell block onto a color component quadruple forming a sample of the color image, the color component quadruple comprising three color component values of a target color space, and one pseudo color component value, and subject the color image to a multi-component picture encoding to obtain a compressed data stream.

Abstract: The invention provides a light-field camera for capturing multiple views of a scene, representing samples of a light-field, having: a primary camera configured for capturing a primary digital two-dimensional image of the scene; a two-dimensional camera array having a plurality of secondary cameras, each of the secondary cameras being configured for capturing a secondary digital two-dimensional image of the scene to produce at least one set of secondary digital two-dimensional images of the scene; a semitransparent mirror arranged such that an incident light beam originating from the scene is split up in a first partial light beam, directed to the primary camera, and a second partial light beam, directed to the camera array; and a processing unit configured for receiving the primary digital two-dimensional image and the at least one set of secondary digital two-dimensional images and configured for computing depth information for the primary digital two-dimensional image or a digital two-dimensional image corr

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Abstract: An apparatus for encoding image data, the image data being decomposed into a plurality of different subbands, each subband having a plurality of coefficients, wherein a precinct has different sets of coefficients from different subbands, wherein two sets of coefficients of a first precinct belong to a first spatial region of an image represented by the image data, the apparatus having: a processor for determining, for each group of coefficients within a set, a greatest coded line index (GCLI); an encoder for encoding the greatest coded line indices associated with a first set of the first precinct in accordance with a first encoding mode, and for encoding the greatest coded line indices associated with a second set of the first precinct in accordance with a second encoding mode, the second encoding mode being different from the first encoding mode; and an output interface for outputting an encoded image signal having data on the encoded greatest coded line indices and data on the coefficients.

Abstract: The invention relates to an integrated circuit comprising: a row of sink cells, a first driver cell, a second driver cell, an interconnect line connecting the first driver cell to the sink cells of the row; and a shunt line connecting the second driver cell to a point between ends of the interconnect line, wherein a segment of the interconnect line between the point and the first driver cell is bigger than 60% of a length the interconnect line and less than 80% of the length of the interconnect line.

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Abstract: A more effective confidence/uncertainty measure determination for disparity measurements is achieved by performing the determination on an evaluation of a set of disparity candidates for a predetermined position of a first picture at which the measurement of the disparity relative to the second picture is to be performed, and if this evaluation involves an accumulation of a contribution value for each of this set of disparity candidates, which contribution values depends on the respective disparity candidate and a dissimilarity to the second picture which is associated with the respective disparity candidate according to a function which has a first monotonicity with a dissimilarity associated with the respective disparity candidate, and a second monotonicity, opposite to the first monotonicity, with an absolute difference between the respective disparity candidate and a predetermined disparity having a minimum dissimilarity associated therewith among dissimilarities associated with the set of disparity candi

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Abstract: Concepts are presented herein how to efficiently create a suitable palette for low complexity image and video coding. A combination of the palette coding with transform coding is feasible.

Abstract: Transform block coding is performed very efficiently in terms of computational complexity and compression ratio, by coding the magnitude bits of the transform coefficients distributed in a matrix, in which the magnitude bits of the spectral coefficients are arranged column-wise with the spectral coefficients of the transform block ordered along a row direction of the matrix. That is, magnitude bits within a certain column of the matrix belong to a certain spectral coefficient, while magnitude bits within a certain row of the matrix belong to a certain bit plane. In this configuration, the distribution of non-zero magnitude bits may be condensed towards one corner of the matrix, corresponding to, for instance, the least significant bit plane and corresponding to, by using a scan order among the transform coefficients which sorts the transform coefficients generally in a manner from lowest to highest frequency, the lowest frequency. Various low complexity variants are presented.

Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.