Abstract: A computer system may obtain a first schematic design netlist for a first IC design and a second schematic design netlist for a second IC design. The computer system may normalize the first netlist and the second netlist. The computer system may determine that the normalized first netlist is the same as the normalized second netlist. The computer system may obtain a first layout design data for the first IC design and a second layout design data for the second IC design. The computer system may determine that the first layout data is the same as the second layout data. The computer system may copy a sign-off data of the first IC design to the second IC design.

Abstract: An integrated circuit includes a static random access memory array. The static random access memory array includes at least two cores, wherein only one of the cores is written at a time. The integrated circuit further includes a tristate driver. The tristate driver is configured to apply a high impedance state to one of the cores that is not being written. A corresponding electronic dataset product includes a description for the integrated circuit expressed in a hardware description language. A corresponding computer-implemented method generates an electronic description for the integrated circuit expressed in a hardware description language.

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Abstract: A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Abstract: The invention relates to an integrated circuit comprising: a row of sink cells, a first driver cell, a second driver cell, an interconnect line connecting the first driver cell to the sink cells of the row; and a shunt line connecting the second driver cell to a point between ends of the interconnect line, wherein a segment of the interconnect line between the point and the first driver cell is bigger than 60% of a length the interconnect line and less than 80% of the length of the interconnect line.

Abstract: A through-silicon via access device (TSVAD) for establishing an electrical connection to a through-silicon via (TSV) located in a planar stack of semiconductor chips is disclosed. The TSVAD may include a switching circuit, having a conductive pad terminal, a TSV terminal, an input terminal coupled to a sending logic circuit, an output terminal coupled to a receiving logic circuit, and logic devices to, in response to control signals, couple the TSV terminal to the conductive pad terminal, in one configuration, and couple the TSV terminal to another terminal in another configuration. The TSVAD may also include a control circuit to generate control signals to cause an input selection circuit to drive a signal from the sending logic circuit onto the input terminal, and to cause an output selection circuit to drive a logic signal from the output terminal to the receiving logic circuit.

Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Abstract: A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Abstract: The invention provides a light-field camera for capturing multiple views of a scene, representing samples of a light-field, having: a primary camera configured for capturing a primary digital two-dimensional image of the scene; a two-dimensional camera array having a plurality of secondary cameras, each of the secondary cameras being configured for capturing a secondary digital two-dimensional image of the scene to produce at least one set of secondary digital two-dimensional images of the scene; a semitransparent mirror arranged such that an incident light beam originating from the scene is split up in a first partial light beam, directed to the primary camera, and a second partial light beam, directed to the camera array; and a processing unit configured for receiving the primary digital two-dimensional image and the at least one set of secondary digital two-dimensional images and configured for computing depth information for the primary digital two-dimensional image or a digital two-dimensional image corr

Abstract: A through-silicon via access device (TSVAD) for establishing an electrical connection to a through-silicon via (TSV) located in a planar stack of semiconductor chips is disclosed. The TSVAD may include a switching circuit, having a conductive pad terminal, a TSV terminal, an input terminal coupled to a sending logic circuit, an output terminal coupled to a receiving logic circuit, and logic devices to, in response to control signals, couple the TSV terminal to the conductive pad terminal, in one configuration, and couple the TSV terminal to another terminal in another configuration. The TSVAD may also include a control circuit to generate control signals to cause an input selection circuit to drive a signal from the sending logic circuit onto the input terminal, and to cause an output selection circuit to drive a logic signal from the output terminal to the receiving logic circuit.

Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Abstract: A through-silicon via access device (TSVAD) for establishing an electrical connection to a through-silicon via (TSV) located in a planar stack of semiconductor chips is disclosed. The TSVAD may include a switching circuit, having a conductive pad terminal, a TSV terminal, an input terminal coupled to a sending logic circuit, an output terminal coupled to a receiving logic circuit, and logic devices to, in response to control signals, couple the TSV terminal to the conductive pad terminal, in one configuration, and couple the TSV terminal to another terminal in another configuration. The TSVAD may also include a control circuit to generate control signals to cause an input selection circuit to drive a signal from the sending logic circuit onto the input terminal, and to cause an output selection circuit to drive a logic signal from the output terminal to the receiving logic circuit.

Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Abstract: A through-silicon via access device (TSVAD) for establishing an electrical connection to a through-silicon via (TSV) located in a planar stack of semiconductor chips is disclosed. The TSVAD may include a switching circuit, having a conductive pad terminal, a TSV terminal, an input terminal coupled to a sending logic circuit, an output terminal coupled to a receiving logic circuit, and logic devices to, in response to control signals, couple the TSV terminal to the conductive pad terminal, in one configuration, and couple the TSV terminal to another terminal in another configuration. The TSVAD may also include a control circuit to generate control signals to cause an input selection circuit to drive a signal from the sending logic circuit onto the input terminal, and to cause an output selection circuit to drive a logic signal from the output terminal to the receiving logic circuit.

Abstract: A mechanism is provided for efficiently recycling a charge from a power domain that is discharging. A side of a discharging power domain normally coupled to a voltage supply is disconnected from the voltage supply. The side of the precharging power domain normally coupled to the voltage supply is currently disconnected from the voltage supply. The side of the discharging power domain normally coupled to the voltage supply is connected to a side of the precharging power domain normally coupled to the voltage supply. A side of the discharging power domain normally coupled to the ground is disconnected from ground. The side of the discharging power domain normally coupled to ground is connected to the voltage supply, thereby precharging the precharging power domain with the charge from the discharging power domain that would normally be lost due to leakage.