Abstract: A semiconductor component has a cell array formed in a semiconductor body with a number of identical transistor cells and at least one edge cell formed at an edge of the cell array. Each of the transistor cells has a control electrode, which is formed in a trench, and the edge cell has a field plate, which is formed in a trench, with a distance between the trench of the edge cell and the trench of the immediately adjacent transistor cell being less than the distance between a trench of a transistor cell and the trench of an immediately adjacent transistor cell in the cell array.

Abstract: The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD of the transistor configuration is reduced by the shielding electrode located in the edge region.

Abstract: The present invention relates to a semiconductor arrangement with a MOS transistor which has a gate electrode (40), arranged in a trench running in the vertical direction of a semiconductor body (100), and a Schottky diode which is connected in parallel with a drain-source path (D-S) and is formed by a Schottky contact between a source electrode and the semiconductor body.

Abstract: In a process for coating a substrate, a texture (4) is created in a portion of its surface. A first layer (5) to be applied on the surface of the substrate adheres better to the texture (4) than it does to a surface area located outside of the texture (4). Then, the layer (5) is applied to the surface of the substrate and after that, areas of the layer projecting laterally beyond the texture (4) are mechanically removed. The material of the texture (4) contains at least one chemical element or a compound, which the layer (5) does not have or has only in a smaller concentration than the material of the texture (4). On the first layer (5), at least one second layer (7) is then applied which does not have the chemical element or compound contained in the material of the texture (4), or it has it only in a smaller concentration than the material of the texture (4).

Abstract: A semiconductor component (1a) has a highly-doped substrate (4) of a first type of doping into which a highly-doped layer (15) of a second type of doping is introduced in some areas to form a pn Zener junction (16), and a low-doped area (17) of the second type of doping extends from this highly-doped layer (15) in the substrate (4) into an epitaxial layer (5) as far as the substrate (4) of the epitaxial layer (5). A Schottky metal (11) at least partially covering the low-doped, diffused area (17) is applied to the side of the epitaxial layer (5) facing away from the substrate (4) to form a Schottky junction (18) between this area (17) and the Schottky metal (11) and another Schottky junction (13) between the Schottky metal and the epitaxial layer (5). Due to the series connection of the oppositely polarized Zener diode and Schottky diode, a low temperature coefficient is achieved.

Abstract: The invention relates to an overvoltage protection device and to a method for fabricating such a device. A substrate (1) is provided with a first electrode layer (2), above which extends a second electrode layer (3) which is separated from the first electrode layer (2) by a distance (d) determined by the thickness of a spacing layer (4). The spacing layer (4) has an opening (5) which forms a cavity (6) between the electrode layers (2, 3).