Abstract: A substrate comprising a core layer, at least one first dielectric layer coupled to a first surface of the core layer, at least one second dielectric layer coupled to a second surface of the core layer, a plurality of interconnects located at least partially in the at least one first dielectric layer; a region comprising a plurality of block interconnects of an interconnect block; and a solder resist layer coupled to the at least one first dielectric layer.

Abstract: A package comprising an integrated device; and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate comprises a core layer comprising a cavity; a region comprising a passive component block located at least partially in the cavity of the core layer, wherein the passive component block comprises a first passive device and a second passive device; at least one dielectric layer coupled to the core layer; and a plurality of interconnects located at least partially in the at least one dielectric layer.

Abstract: A substrate comprising at least one dielectric layer, and a plurality of interconnects located at least partially in the at least one dielectric layer, wherein the plurality of interconnects include a plurality of via interconnects, and wherein the plurality of via interconnects include a first via interconnect comprising a first via wall that is approximately vertical.

Abstract: Hybrid package substrates employing film metallization layers with outer pre-impregnated (PPG) region(s) to support high density bump and wire bond connections for respective bump and wire bond connected dies in the IC package, and related hybrid integrated circuit (IC) packages and fabrication methods are disclosed. The package substrate includes film metallization layers of a softer, flexible material that can more easily be patterned to support formation of high density, reduced pitch metal interconnects to support finer bump pitch connections to a bottom, first die(s) in a die region of the package substrate. The package substrate also includes one or more PPG regions a PPG metallization layer(s) adjacent to the die region of the package substrate that reinforces the film metallization layers and also supports the formation of wire bond pads for wire bond connections to an upper, second die(s) in the hybrid IC package.

Abstract: A device includes a core including an upper core dielectric layer, a lower core dielectric layer, a central core dielectric layer contacting the upper core dielectric layer and the lower core dielectric layer, and a passive electronic component embedded within the central core dielectric layer. The device includes an upper laminate stack coupled to the upper core dielectric layer. The upper laminate stack includes upper metal layers and contact pads configured to electrically connect a die to the passive electronic component by way of conductive paths defined by the set of upper metal layers. The device includes a lower laminate stack coupled to a bottom surface of the lower core dielectric layer. The lower laminate stack includes lower metal layers and a set of lower dielectric layers disposed between adjacent metal layers of the set of lower metal layers.

Abstract: A device includes a bottom substrate including first conductors, a top substrate including second conductors, and a first die disposed between the bottom substrate and the top substrate. The first die includes circuitry and first contacts electrically connected to the circuitry and to the first conductors. The device also includes a redistribution die disposed between the bottom substrate and the top substrate adjacent to the first die. The redistribution die includes second contacts electrically connected to the first contacts through the first conductors and third contacts electrically connected to the second conductors. The redistribution die also includes redistribution traces electrically connected to the second contacts and to the third contacts. The top substrate includes fourth contacts electrically connected through the second conductors to the third contacts to define one or more signal paths between the fourth contacts and the first die.

Abstract: A substrate includes a core layer and one or more metallization layers. The core layer provides stabilization to the substrate to reduce or avoid warpage. The core layer may include a glass material weaved throughout the core to provide stabilization and avoid warpage. A metallization layer adjacent to the core layer in the substate includes an insulation layer and the embedded metal structure(s) that is positioned from the core layer. The thickness of the insulation layer is greater than the embedded metal structure so that a surface of the embedded metal structure is positioned at least at a length from the surface of the glass material. This can avoid or reduce the risk of the embedded metal structure electrically shorting to another metal structure in the substrate through the core layer.

Abstract: Disclosed are devices in which a die, such as a system-on-chip (SoC) die is attached to an interposer with a mold. Unlike convention devices, the contact area for adhesion is increased by providing vertical surfaces in addition to lateral surfaces for attachment. In so doing, possibility of delamination is decreased significantly.

Abstract: Package substrate with metallization layer(s) that includes an additional metal pad layer to facilitate reduced via size for reduced bump pitch, and related integrated circuit (IC) packages and fabrication methods. An additional metal pad(s) is provided in an insulating layer of a metallization layer(s) of the package substrate in which a via(s) is formed to reduce vertical connectivity distance between metal interconnects in adjacent metallization layers electrically coupled together by the via. This can reduce the aspect ratio and size of the via thereby allowing metal interconnects that are electrically coupled to the via to also be reduced in size (e.g., width) while still supporting an aligned, low resistance connection between the via(s) and the metal interconnects. Being able to reduce the size (e.g., width) of the metal interconnects can reduce bump pitch of the package substrate, which can facilitate a higher density of die/bump connections to the package substrate.

Abstract: Disclosed is a stack via structure in which a plurality of vias are stacked over each other. At least one via is a via that has a recess formed from a top surface thereof. Another via above the via is formed such that a bottom portion of the another via is in the recess of the via. In this way, no capture pad is needed between the via and the another via. Also, contact area between the via and the another via is enhanced.

Abstract: In an aspect, an apparatus includes a package. The package includes a substrate, a plurality of components located on a top surface of the substrate, a plurality of ball pads located on a bottom surface of the substrate, a plurality of balls, and a plurality of test pads located on the bottom surface of the substrate. Individual balls of the plurality of balls are attached to individual ball pads of the plurality of ball pads.

Abstract: Aspects disclosed in the detailed description include an integrated circuit (IC) package employing a metal block with metal interconnects thermally coupling a semiconductor die (“die”) to an interposer substrate for dissipating thermal energy in the die. The die is coupled to a package substrate to provide signal routing paths to the die. To facilitate additional dies being stacked in the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate. The interposer substrate also includes a metal block which comprises a plurality of metal layers and is thermally coupled to the die and a metal interconnect(s) in the interposer substrate to dissipate thermal energy from the die through the metal block and through the coupled metal interconnect(s).

Abstract: In an aspect, an electronic device is disclosed that includes a substrate comprising a core having an upper planar surface and a lower planar surface, wherein the core includes a cavity extending through the core; an electronic component at least partially disposed in the cavity, wherein the electronic component has an upper planar surface having one or more electronic component terminals; a first cured resin layer, wherein the upper planar surface of the electronic component is at least partially embedded in the first cured resin layer at least at an upper portion of the cavity; and an upper metallization structure disposed over the upper planar surface of the core, wherein the upper metallization structure is configured to provide one or more conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

Abstract: In an aspect, a substrate includes a core that includes a core dielectric and a first conductive pattern on a first surface of the core dielectric, and a first metallization structure over the first surface of the core dielectric. The first metallization structure includes a first dielectric, and the first dielectric has a first opening formed therein. The substrate further includes a first electronic component disposed in the first opening of the first dielectric, and a first adhesive layer coupling the first electronic component with the core.

Abstract: A package comprising a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate comprises a bridge and/or an interposer, an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block and a second plurality of pillar interconnects coupled to the second interconnection portion block.

Abstract: A package comprising a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate comprises an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer at least partially encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block and a second plurality of pillar interconnects coupled to the second interconnection portion block.

Abstract: A substrate(s) for an integrated circuit (IC) package employing a metal core for improved electrical shielding and structural strength. In one aspect, a substrate comprises a core layer. The core layer comprises a metal core, the metal core having a first surface and a second surface opposite the first surface. The core layer further comprises a first insulation layer on the first surface and a second insulation layer on the second surface. The substrate further comprises a first metallization structure adjacent to the first insulation layer and a second metallization structure adjacent to the second insulation layer. The metal core provides electrical shielding of signals/power routed through the metal core for noise coupling reduction allowing a higher density of signal and power paths to be supported in substrate, while also strengthening structural integrity to prevent or reduce warpage in the IC package.

Abstract: Integrated circuit (IC) package employing metal posts thermally coupling a die to an interposer substrate for dissipating thermal energy of the die are disclosed. In one aspect, the IC package includes a metal post(s) thermally coupled to the die. The metal post(s) is attached to metal interconnect(s) (e.g., metal trace, metal pad, metal line, metal plate) in the interposer substrate. In this manner, as thermal energy is generated in the die, this thermal energy dissipates through the metal post(s) and through the coupled metal interconnect(s) into the interposer substrate. Thus, metal interconnects, which are an available feature in an interposer substrate fabrication process, are deployed to form the foundation upon which metal posts are fabricated and thermally coupled to the die to provide heat dissipation for the die in the IC package.

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes (i) a first cored substrate portion comprising a first core layer comprising a first cavity, a first integrated device located in the first cavity of the first core layer, and a first dielectric layer encapsulating the first integrated device; and (ii) a second cored substrate portion comprising a second core layer comprising a second cavity, a second integrated device located in the second cavity of the second core layer and a second dielectric layer encapsulating the second integrated device.

Abstract: A package comprising a substrate and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first plurality of interconnects, and a first integrated device located at least partially in the substrate. The first integrated device is coupled to the first plurality of interconnects through a first plurality of solder interconnects. The second integrated device is coupled to the first plurality of interconnects through a second plurality of solder interconnects.