Abstract: An interposer having one or more hollow electrical contact buttons disposed in a carrier. The interposer is formed by disposing sacrificial posts in vias of the carrier. The electrical contact buttons are formed on the sacrificial posts by a metallizing process in desired pattern using a mask. The sacrificial posts are made of a material that thermally decomposes upon application of heat without altering the carrier or the electrical contact buttons.

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Abstract: An interposer having one or more hollow electrical contact buttons disposed in a carrier. The interposer is formed by disposing sacrificial posts in vias of the carrier. The electrical contact buttons are formed on the sacrificial posts by a metallizing process in desired pattern using a mask. The sacrificial posts are made of a material that thermally decomposes upon application of heat without altering the carrier or the electrical contact buttons.

Abstract: An interposer having one or more hollow electrical contact buttons disposed in a carrier. The interposer is formed by disposing sacrificial posts in vias of the carrier. The electrical contact buttons are formed on the sacrificial posts by a metallizing process in desired pattern using a mask. The sacrificial posts are made of a material that thermally decomposes upon application of heat without altering the carrier or the electrical contact buttons.

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP.

Abstract: A method is provided for the manufacture of micro-structures, such as micro-electromechanical structures (MEMS) or silicon optical benches (SiOB). The method includes using a single mask to pattern two or more cavity areas to be etched into a substrate in different etching steps, and then selectively choosing the cavity areas for etching. In a preferred embodiment, the method includes patterning a substrate to identify a plurality of cavity areas to be etched into the substrate and filling at least one of the cavity areas with a distinctive filler material. Filler material is chemically distinctive in the sense that it can be etched selectively with respect to the other filling materials. At least one of the cavity areas containing a distinctive filler material is then chosen based at least in part on the distinctive filler material. The chosen cavity area is then etched.

Abstract: A method is provided for the manufacture of micro-structures, such as micro-electromechanical structures (MEMS) or silicon optical benches (SiOB). The method includes using a single mask to pattern two or more cavity areas to be etched into a substrate in different etching steps, and then selectively choosing the cavity areas for etching. In a preferred embodiment, the method includes patterning a substrate to identify a plurality of cavity areas to be etched into the substrate and filling at least one of the cavity areas with a distinctive filler material. Filler material is chemically distinctive in the sense that it can be etched selectively with respect to the other filling materials. At least one of the cavity areas containing a distinctive filler material is then chosen based at least in part on the distinctive filler material. The chosen cavity area is then etched.

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

Abstract: A method is provided for the manufacture of micro-structures, such as micro-electromechanical structures (MEMS) or silicon optical benches (SiOB). The method includes using a single mask to pattern two or more cavity areas to be etched into a substrate in different etching steps, and then selectively choosing the cavity areas for etching. In a preferred embodiment, the method includes patterning a substrate to identify a plurality of cavity areas to be etched into the substrate and filling at least one of the cavity areas with a distinctive filler material. Filler material is chemically distinctive in the sense that it can be etched selectively with respect to the other filling materials. At least one of the cavity areas containing a distinctive filler material is then chosen based at least in part on the distinctive filler material. The chosen cavity area is then etched.

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP.

Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP.

Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP.

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.