Abstract: Embodiments of the invention generally related to arrangements of decoupling capacitor arrays in an integrated circuit. A decoupling capacitor array may include a plurality of bit lines that are electrically coupled to each other, a plurality of word lines that are electrically coupled to each other, and a plurality of decoupling capacitors, each decoupling capacitor coupled to a respective bit line and word line. The decoupling capacitor array may further include an access circuit electrically coupled to the plurality of word lines and a power grid, the access circuit being configured to either connect or disconnect the decoupling capacitor array to the power grid based on a control signal.

Abstract: A method of operating a system including a memory device. The method includes, upon receiving a request for an internal hidden refresh for the memory device, latching external command, address, and data information for the memory device. The method further includes placing the memory device in a standby state and during the standby state, performing the internal hidden refresh. The method further includes, after performing the internal hidden refresh, placing the memory device in a state corresponding to the latched external command, address, and data information for the memory device.

Abstract: Embodiments of the invention generally provide methods, systems, and apparatus for testing decoupling capacitors of an integrated circuit. A decoupling capacitor may be disconnected from the power grid of the integrated circuit during testing. The voltage of the decoupling capacitor may be compared to the voltage of a reference capacitor to determine whether the decoupling capacitor is defective. If the decoupling capacitor is determined to be defective, the decoupling capacitor is not reconnected to the power grid, thereby reducing the leakage currents in the integrated circuit.

Abstract: Embodiments of the invention generally related to arrangements of decoupling capacitor arrays in an integrated circuit. A decoupling capacitor array may include a plurality of bit lines that are electrically coupled to each other, a plurality of word lines that are electrically coupled to each other, and a plurality of decoupling capacitors, each decoupling capacitor coupled to a respective bit line and word line. The decoupling capacitor array may further include an access circuit electrically coupled to the plurality of word lines and a power grid, the access circuit being configured to either connect or disconnect the decoupling capacitor array to the power grid based on a control signal.

Abstract: A method of inputting data to an integrated circuit is disclosed. A plurality of data signals are serially received from a source external to the integrated circuit. A strobe signal is derived from the plurality of data signals. The deriving is done by circuitry within the integrated circuit. The data signals can be latched at an input of the integrated circuit using the strobe signal that was derived within the integrated circuit.

Abstract: Methods and circuits for detecting variations in signal propagation rates within an electronic device, and for adjusting the output timing of the device in response to the variations in signal propagation rates. According to an embodiment of the invention, a signal may be propagated through an uncompensated delay chain and a compensated delay chain. If the signal passes through the compensated chain slower than through the uncompensated delay chain, then the device may delay a clock signal such that the output timing of the device will remain within the specification parameters. In contrast, if the signal passes through the uncompensated delay chain slower than through the compensated delay chain, the device may not delay the received clock signal such that the output timing of the device will remain within specification parameters.

Abstract: Methods and circuits for detecting variations in signal propagation rates within an electronic device, and for adjusting the output timing of the device in response to the variations in signal propagation rates. According to an embodiment of the invention, a signal may be propagated through an uncompensated delay chain and a compensated delay chain. If the signal passes through the compensated chain slower than through the uncompensated delay chain, then the device may delay a clock signal such that the output timing of the device will remain within the specification parameters. In contrast, if the signal passes through the uncompensated delay chain slower than through the compensated delay chain, the device may not delay the received clock signal such that the output timing of the device will remain within specification parameters.

Abstract: Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse.

Abstract: A dynamic random access memory device includes an array of dynamic random access memory cells subdivided into a group of blocks. Each of the blocks of memory cells can be independently operated in either a single cell mode or a twin cell mode.

Abstract: A dynamic random access memory device includes an array of dynamic random access memory cells subdivided into a group of blocks. Each of the blocks of memory cells can be independently operated in either a single cell mode or a twin cell mode.

Abstract: A method of inputting data to an integrated circuit is disclosed. A plurality of data signals are serially received from a source external to the integrated circuit. A strobe signal is derived from the plurality of data signals. The deriving is done by circuitry within the integrated circuit. The data signals can be latched at an input of the integrated circuit using the strobe signal that was derived within the integrated circuit.

Abstract: Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse.

Abstract: Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse.

Abstract: A serial shift register and method for simultaneously storing bits of data and a serially advancing pointer is provided. In one embodiment, each stage of the shift register may have only two latches: one to store a bit of pointer information and one to store data.

Abstract: Embodiments are provided in which a method and an apparatus for sequentially programming electrical fuses are described. A fuse pointer is advanced to point to (i.e., select) the fuses sequentially. When the fuse pointer reaches (i.e., points to) a fuse that is not to be blown, the fuse pointer automatically and asynchronously (e.g. not synchronized to a programming clock signal) skips the fuse. On the other hand, when the fuse pointer reaches a fuse that is to be blown, the fuse pointer stops and the fuse is blown synchronously (e.g., in response to the programming clock signal). After the blow, the fuse pointer advances to the next fuse and the process described above repeats, until the last fuse is programmed. A fuse latch circuit associated with the blown fuse may be optionally reset prior to advancing the fuse pointer.

Abstract: Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse.

Abstract: Embodiments are provided in which a method and an apparatus for sequentially programming electrical fuses are described. A fuse pointer is advanced to point to (i.e., select) the fuses sequentially. When the fuse pointer reaches (i.e., points to) a fuse that is not to be blown, the fuse pointer automatically and asynchronously (e.g. not synchronized to a programming clock signal) skips the fuse. On the other hand, when the fuse pointer reaches a fuse that is to be blown, the fuse pointer stops and the fuse is blown synchronously (e.g., in response to the programming clock signal). After the blow, the fuse pointer advances to the next fuse and the process described above repeats, until the last fuse is programmed. A fuse latch circuit associated with the blown fuse may be optionally reset prior to advancing the fuse pointer.

Abstract: A serial shift register and method for simultaneously storing bits of data and a serially advancing pointer is provided. In one embodiment, each stage of the shift register may have only two latches: one to store a bit of pointer information and one to store data.

Abstract: The present invention relates to a substantially water-free sizing composition, an aqueous sizing dispersion and a process for the production of paper and board. The composition or dispersion comprises a cellulose reactive sizing agent and a copolymer which is prepared from a monomer mixture comprising one or more olefins and one or more derivatives of unsaturated carboxylic acids. More specifically, the composition or dispersion comprises a copolymer prepared form a monomer mixture comprising one or more &agr;-olefins and one or more derivatives of &agr;,&bgr;-unsaturated dicarboxylic acids.