Abstract: The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.

Abstract: Test circuit for testing a synchronous memory circuit having a frequency multiplication circuit which multiplies a clock frequency of a low-frequency clock signal received from an external test unit by a particular frequency multiplication factor a test data generator which produces test data on the basis of data control signals received from the external test unit and outputs them to a data output driver a first signal delay circuit for delaying the test data which are output by the test data generator by an adjustable first delay time, a second signal delay circuit for delaying data which are read out of the synchronous memory circuit and are received by a data input driver in the test circuit by an adjustable second delay time, and having a data comparison circuit which compares the test data produced by the test data generator with the data read out of the memory circuit and, on the basis of the comparison result, outputs an indicator signal to the external test unit which indicates whether the synchronou

Abstract: A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.

Abstract: The invention relates to the internal exhaust-gas recirculation in an internal combustion engine with gas exchange valves periodically controlled by a camshaft (22) in accordance with the four-stroke principle, in which, during the gas exchange exhausting of exhaust gas from the respective cylinder (1) into the exhaust duct (5), an intake valve (2) associated with the respective cylinder (1) is open in a crank angle range after top dead center of the ignition of the gas mixture present in the cylinder (1), in order to exhaust part of the exhaust gas into an intake duct (3), so that during the next gas exchange intake both fresh gas and exhaust gas are taken in from the intake duct (3), the respective intake valve (2) being actuated during the gas exchange exhausting independently of the periodic gas exchange intake, and the additional opening of the respective intake valve (2) being carried out in the range from 110 to 150% of the opening angle of the start of opening of the exhaust duct (5) by the exhaust va

Abstract: A casing for an optical set-up is described, with the casing comprising a cutout adapted for accommodating an optical component, wherein the geometry of the cutout is adapted for mounting the optical component from the exterior of the casing, and wherein the geometry of the cutout is adapted for mechanically fastening the optical component by means of an elastic force exerted radially upon the outer surface of the optical component.

Abstract: A method of manufacturing a flow cell with a cell housing having a bore for the passage of sample, and with an inner layer of a totally reflecting polymer material for guiding radiation through the bore for the analysis of the sample, comprises the steps of: a) providing a tube of the polymer material in the bore of the cell housing, and b) applying a force on the walls of the tube from the interior of the tube for pressing the walls of the tube against the cell housing. The force may be applied by any suitable means, for example by drawing a mandrel through the interior of the tube, or by using pressurized gas or liquid. The resulting flow cell has a smooth inner surface with improved optical properties.

Abstract: A cluster includes a plurality of application server instances, a central services instance that includes a message server, and a database. The application server instances each include a dispatcher, a plurality of redundant server nodes, and a socket connection between the dispatcher and each of the server nodes for handling communications relating to processing a client request. A separate socket connection between the message server and each of the server nodes is provided for handling internal communications between the server nodes. Additionally, a third socket connection may be established directly between server nodes.

Abstract: An address generator is provided for generating addresses for testing an addressable circuit. The address generator can include a base address register for buffer-storing a base address. The base address register can be assigned an associated offset register group having a plurality of offset registers for buffer-storing relative address values. Further, the address generator can include a first multiplexer circuit which is dependent on a base register selection control signal, switches through an address buffer-stored in the base address register to a first input of an addition circuit and to an address bus, which is connected to the circuit to be tested. A second multiplexer circuit can be dependent on the base register selection control signal, through-connects the offset register group associated with the through-connected base address register to a third multiplexer circuit, which is dependent on an offset register selection control signal.

Abstract: An analysis cell arranged in a flow path of a fluid to be analyzed includes a cavity adapted for receiving the fluid, a detection unit coupled to the cavity for detecting a property of the fluid, and a curved pipeline for supplying the fluid to the cavity connected to an orifice of the cavity.

Abstract: A system and method of providing logical locking to shared resources in a distributed Java environment. A plurality of Java virtual machines (JVMs) share a lock server. Each JVM includes a lock manager to interact with the lock server. The lock server provides a centralized source of logical locks for shared resources and maintains a lock table of those locks in a shared memory.

Abstract: A method and a configuration for driving one-time operable isolation elements on a semiconductor chip store an item of isolation information for each isolation element to be operated on the chip. In which case, as soon as the isolation information item is present for an isolation element, a one-time operation on the isolation element is begun.

Abstract: The present invention relates to conjugates of synthetic binding units and nucleic acids. The present invention also relates to methods for sorting and immobilizing nucleic acids on support materials using such conjugates by specific molecular addressing of the nucleic acids mediated by the synthetic binding systems. Particularly, the present invention also relates to novel methods of utilizing conjugates of synthetic binding units and nucleic acids to in active electronic array systems to produce novel array constructs from the conjugates, and the use of such constructs in various nucleic acid assay formats. In addition, the present invention relates to various novel forms of such conjugates, improved methods of making solid phase synthesized conjugates, and improved methods of conjugating pre-synthesized synthetic binding units and nucleic acids.

Abstract: A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.

Abstract: Test data generator for generating test data patterns for the testing of a circuit having a frequency multiplication circuit, which increases a low clock frequency of an input clock signal received by a test unit with a specific clock frequency multiplication factor. Also provided is a plurality of data registers for storing test data words read from the data registers, and multiplexer that switches through a test data word read from a data register with the high clock frequency of the output clock signal to a data bus in a way dependent on a register selection control datum of a multi-position register selection control data vector.

Abstract: The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Abstract: A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.

Abstract: A test configuration for the functional testing of a semiconductor chip is described. The semiconductor chip, which can be subjected to a functional test for the purpose of checking the functionality of the semiconductor chip, is disposed on a support material. The semiconductor chip contains a self-test unit for generating test information and for carrying out the functional test. An energy source serves for providing an electrical energy supply from energy that is fed in contactlessly. The energy source is disposed on the support material and is connected to the semiconductor chip for the purpose of providing an energy supply on the semiconductor chip. The test configuration makes it possible to carry out a contactless functional test and to reduce the test costs by virtue of high parallelism during the functional test of a plurality of semiconductor chips.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Abstract: A test circuit is adapted to test circuits having a high-frequency clock signal. The test circuit is positioned between a conventional tester and the circuit to be tested. The test circuit includes a frequency multiplication circuit which multiplies the clock signal of the conventional tester to produce a high-frequency clock signal. The test circuit also receives control signals from the conventional tester. The control signals are output to the circuit to be tested via a bus.