Abstract: A lowermost layer of control chips carries on it layers of memory chips. The memory chips are contacted via looped-through contacts that reach from one side of the other side of the memory chips and they are driven by the control chips that contain the test circuit for the memory chips.

Abstract: The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.

Abstract: A telescopically extendible focusing hood which improves the viewing of the LCD screen of a digital camera in bright surrounding light. The focusing hood can be fixed to the rear wall of the camera, surrounding the LCD screen. The focusing hood preferably has an anti-reflection-coated enlarging lens or glass disk which covers the entire cross-section of the focusing hood in parallel to the fixing plane. In its extended state, the focusing hood can be used with a single lens in the manner of a 35 mm camera finder. When the enlarging lens is pushed in, the focusing hood can be used with two lenses for assessing the image.

Abstract: Test circuit for testing a circuit to be tested, having a test data generator, which generates test data in a manner dependent on data control signals which are received via data control lines from an external test unit, a data output driver for outputting the generated test data via data line pairs of a differential data bus to the circuit to be tested, a data input circuit for receiving data that are read from the circuit to be tested and transmitted via the data line pairs of the differential data bus, a data comparison circuit, which compares the generated data and the read-out data and, in a manner depend at on the comparison result transmits an indication signal, which indicates whether the circuit to be tested is functional, to the external test unit via an indication signal line.

Abstract: A passenger chair or a group of passenger chairs, particularly in an aircraft cabin, is equipped with a convenience device that includes an open storage bail which can hold only flat articles but not waste material, and a waste container for holding waste material but not flat articles. The storage bail and waste container form either a mounting unit or retrofit kit or are separate components. In both instances the mounting unit and the separate components are secured to a back facing area of a chair or group of chairs. The separate components are preferably so constructed that individual retrofit kits are provided.

Abstract: A seating space such as an aircraft passenger cabin has rows of seats along an aisle, identified by a row number and a seat location letter. A seat row indicator is arranged on the side flank of the seat back of each aisle seat, at the corner where the side flank and upper edge of the seat back meet. A seat location indicator is arranged at the middle of the upper edge of the seat back of each seat. The row numbers and seat letters are indicated on or in the indicators by paint, printing, engraving, inserts, illumination or tactile indicia. The indicators are conspicuous and easily visible to a passenger standing or walking in the aisle without bending or leaning over. Boarding of the aircraft is facilitated and expedited. Emergency evacuation is assisted by appropriate illumination of the indicators.

Abstract: An integrated semiconductor memory device that can be subjected to a memory cell test in order to determine functional and defective memory cells includes addressable normal memory cells, a first redundancy unit having first addressable redundant memory cells and optically programmable switches for replacing an address of a defective normal memory cell by the address of a first redundant memory cell, and a second redundancy unit having second addressable redundant memory cells and electrically programmable switches for replacing an address of a defective normal memory cell by the address of a second redundant memory cell. The second redundancy unit can be connected by the activation of an irreversibly programmable switch, which enables a simplified functional test at the wafer level.

Abstract: The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

Abstract: A method of manufacturing a flow cell with a cell housing (11) having a bore for the passage of sample, and with an inner layer of a totally reflecting polymer material (17) for guiding radiation through the bore for the analysis of the sample, comprises the steps of a) providing a tube (10) of said polymer material in the bore (30) of the cell housing (11), and b) applying a force on the walls of said tube (10) from the interior of the tube for pressing the walls of the tube against the cell housing (11). The force may be applied by any suitable means, for example by drawing a mandrel (15) through the interior of the tube, or by using pressurized gas or liquid. The resulting flow cell has a smooth inner surface with improved optical properties.

Abstract: An integrated semiconductor circuit, in particular a semiconductor memory configuration, which can be operated in various operating modes and which has an apparatus for switching between these operating modes is described. The semiconductor circuit has a switching apparatus with at least one fuse unit, which can be blown and programmed from the exterior.

Abstract: An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

Abstract: Test circuit for testing a synchronous circuit (3) which is clocked with an operating clock signal with a high operating clock frequency, having:

Abstract: Test circuit for testing a synchronous memory circuit Test circuit for testing a synchronous memory circuit (3) having a frequency multiplication circuit (4) which multiplies a clock frequency of a low-frequency clock signal received from an external test unit by a particular frequency multiplication factor in order to produce a high-frequency clock signal for the synchronous memory chip (3) to be tested, a test data generator (16) which produces test data on the basis of data control signals received from the external test unit (2) and outputs them to a data output driver (14) in order to write them to the synchronous memory circuit (3) to be tested, a first signal delay circuit (19) for delaying the test data which are output by the test data generator (16) by an adjustable first delay time, a second signal delay circuit (24) for delaying data which are read out of the synchronous memory circuit (3) to be tested and are received by a data input driver (15) in the test circuit (1) by an adjustable second del

Abstract: Test circuit for testing a circuit to be tested, having a test data generator, which generates test data in a manner dependent on data control signals which are received via data control lines from an external test unit, a data output driver for outputting the generated test data via data line pairs of a differential data bus to the circuit to be tested, a data input circuit for receiving data that are read from the circuit to be tested and transmitted via the data line pairs of the differential data bus, a data comparison circuit, which compares the generated data and the read-out data and, in a manner dependent on the comparison result, transmits an indication signal, which indicates whether the circuit to be tested is functional, to the external test unit via an indication signal line, each data line pair of the differential data bus, between the circuit to be tested and the test circuit, having a first data signal line for the transmission of a data signal and a second data signal line for the transmissio

Abstract: Test circuit for testing a circuit (3) which is clocked with a high-frequency clock signal and needs to be tested, where the test circuit (1) has:

Abstract: An aircraft passenger chair has a support frame, a seat and a backrest. A position adjustment mechanism is coupled between the frame and the backrest by a unidirectional force transmission to permit tilting the backrest clockwise forward into a parking position while simultaneously shifting the seat backward independently of the position adjustment mechanism to increase the space between two rows of seats. Operating the position adjustment mechanism tilts the backrest counterclockwise from an upright position into a rest position and returns the backrest into its upright position. Bringing the backrest into the parking position and shifting the seat simultaneously backward is independent of tilting the backrest into a rest position. Similarly returning the backrest and the seat into the respective normal position is also independent of returning the backrest from the rest position into the normal position.

Abstract: Address generator for generating addresses for testing an addressable circuit (2), having: at least one base address register (12) for buffer-storing a base address, the base address register (12) in each case being assigned an associated offset register group (13) having a plurality of offset registers for buffer-storing relative address values; a first multiplexer circuit (38), which, in a manner dependent on a base register selection control signal, switches through an address buffer-stored in the base address register (12) to a first input (59) of an addition circuit (60) and to an address bus (3), which is connected to the circuit (2) to be tested; a second multiplexer circuit (17), which, in a manner dependent on the base register selection control signal, through-connects the offset register group (13) associated with the through-connected base address register (12) to a third multiplexer circuit (25), which, in a manner dependent on an offset register selection control signal, through-connects an offs

Abstract: Test data generator for generating test data patterns for the testing of a circuit having a frequency multiplication circuit, which increases a low clock frequency of an input clock signal received by a test unit with a specific clock frequency multiplication factor. Also provided is a plurality of data registers for storing test data words read from the data registers, and multiplexer that switches through a test data word read from a data register with the high clock frequency of the output clock signal to a data bus in a way dependent on a register selection control datum of a multi-position register selection control data vector.

Abstract: The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a metallization region (10a) comprising a first metal in the circuit substrate (1); providing a first insulation layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15′) above the resulting structure; depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; polishing-back of the second insulating layer (35) and of the functional layer (15′) in order to uncover the surface of the first insulating layer (25); forming a contact (11a′) in the second insulating layer (35) inside the opening (13) in order to make contact with the functional layer (15′); and providing an interconnect (40a) for electrical connecti

Abstract: A connection element in an integrated circuit having a layer structure disposed between two conductive structures. The layer structure is formed by an insulating layer, which can be destroyed by application of a predetermined voltage, and a silicon layer. The insulating layer adjoins a first conductive structure made of tungsten.