Abstract: A method for tracking transitions in a bit stream of a signal includes taking a first sample of said bit stream at a first sampling point of a first sampling sequence, taking a second sample of said bit stream at a second sampling point of said first sampling sequence, and taking a third sample of said bit stream at a third sampling point of said first sampling sequence, wherein said second sampling point is adjusted so that within a first time period, defined by said first and said second sampling points, the number of transitions in said bit stream is equal to the number of transitions within a second time period, defined by said second and said third sampling points.

Abstract: An analog signal is sampled; a reference signal synchronized to the sampling is generated; the sampling result is compared to said reference signal; the time interval from the sampling point to the time the comparison result satisfies the prescribed condition is acquired; and the amplitude of the digital representation is determined from the acquired time interval and knowledge of the reference signal.

Abstract: The present invention relates to a method for evaluating an output signal of a Device Under Test, wherein said Device Under Test outputs said output signal in response to an input signal provided by an Automated Test Equipment, said method including the steps of: generating a difference signal representing the difference between said output signal of said Device Under Test and a reference signal, integrating said difference signal during a clock period respectively, resulting in an integrated difference signal, and evaluating said integrated difference signal with regard to a bit level to be assigned to said output signal of said Device Under Test during the respective clock period.

Abstract: A method for generating an analog signal based on samples representing the analog signal includes feeding the samples into a delta-sigma modulator, the delta-sigma modulator outputting a sequence of bits, and introducing a non-linear time-discrete function into a feedback loop between a quantizer element and a delta element of the delta-sigma modulator, where arguments of the non-linear time-discrete function include a current bit and at least one bit previous to the current bit.

Abstract: The present invention relates to a method for generating jitter in a digital data signal, the digital data signal having a predetermined data pattern being stored in a memory, the method comprising the steps of reading out the digital data signal from the memory using a clock signal provided by a clock source and modulating the clock signal provided by the clock source according to clock-control data, wherein the clock-control data represents the jitter to be generated in the digital data signal read out from the memory.

Abstract: A method for converting a digital signal to an analog signal, said method including a plurality of signal sources, preferably current sources, one or more of said signal sources being variable output signal magnitude sources, said method including the steps of setting the output signal magnitudes of the one or more variable output signal magnitude sources by individual setting signals being input signals for said respective variable output signal magnitude sources, wherein said conversion is adaptable on a per signal basis in response to needs concerning bandwidth and/or accuracy for achieving a trade-off between sample-rate and resolution of said conversion.

Abstract: A method and a corresponding system for converting a digital signal to an analog signal using a plurality of signal sources, preferably current sources, at least two of the signal sources being equal output signal magnitude sources, said method including controlling the equal output signal magnitude sources by a logic circuit, providing a digital input signal to the logic circuit, the digital input signal being derived from the digital signal to be converted, filtering the digital input signal using a filter, the filter having a filter order being adaptable by the logic unit in response to needs concerning bandwidth of the conversion, and summing the outputs of the equal output signal magnitude sources to contribute to the analog signal.

Abstract: An integrated circuit, including a configurable scan architecture used for an integrated circuit test procedure and quality control. The configurable scan chain architecture has the capability of being reconfigured to one of a variety scan chain architectures based on the constraints of the integrated circuit and the testing device. The present invention minimizes the integrated circuit test time by reconfiguring the scan architecture depending on certain constraints such as the latching frequency, the predetermined I/O frequency, the number of available integrated circuit I/O pins, the number of pins required for a proposed scan architecture, and the number of available pins on the testing device. The configurable scan architecture receives configuration signals which indicate which scan chain architecture should be configured on the integrated circuit that is being tested.

Abstract: Using component-level test data to reduce system test. By modeling a system, sensitivity analysis reveals critical components and parameters of those components required to meet system performance parameters. Critical components are tested for these parameters, and these measurements associated with the components. Systems may be assembled which are modeled to meet the system performance parameters based on the model and the measured parameters. Systems may be assembled and calibration coefficients derived and applied from the model and the measured parameters.

Abstract: An analog signal is sampled; a reference signal synchronized to the sampling is generated; the sampling result is compared to said reference signal; the time interval from the sampling point to the time the comparison result satisfies the prescribed condition is acquired; and the amplitude of the digital representation is determined from the acquired time interval and knowledge of the reference signal.

Abstract: The present invention relates to a method for pulse placement to form a binary pulse signal, said binary pulse signal having a constant pulse rate being reciprocal of a constant pulse rate period, comprising the steps of generating a bit clock having a bit clock period of shorter duration than said constant pulse rate period, synthesizing pulses with leading and trailing edges, said leading and trailing edges of said synthesized pulses being placed at N-multiples of said bit clock period within said constant pulse rate period, with N=0, 1, 2, . . , and selecting said bit clock period individually for successive pulses of said binary pulse signal.

Abstract: A wireless data communications link connects a wireless device to a test station. The test station transmits command and control parameters to the wireless device using the wireless data communications link. The command and control parameters place the wireless device in a test mode and test the quality and operations of a radio frequency (RF) link established between the wireless device and the test station. The wireless data communications link is also used to transmit test and control parameters from the wireless device to the test station.

Abstract: The present invention relates to a method for pulse placement to form a binary pulse signal, said binary pulse signal having a constant pulse rate being reciprocal of a constant pulse rate period, comprising the steps of generating a bit clock having a bit clock period of shorter duration than said constant pulse rate period, synthesizing pulses with leading and trailing edges, said leading and trailing edges of said synthesized pulses being placed at N-multiples of said bit clock period within said constant pulse rate period, with N=0, 1, 2, . . . , and selecting said bit clock period individually for successive pulses of said binary pulse signal.

Abstract: A method for generating an analog signal based on samples representing the analog signal, includes feeding the samples into a delta-sigma modulator, the delta-sigma modulator outputting a sequence of bits, and introducing a non-linear time-discrete function into a feedback loop between a quantizer element and a delta element of the delta-sigma modulator, where arguments of the non-linear time-discrete function include a current bit and at least one bit previous to the current bit.

Abstract: A method and apparatus for testing a device using transition timestamp are used to evaluate output signals from the device. The method comprises the steps of performing timing tests on a signal from the device; and independently carrying out bit-level tests on a signal from the device. The independent timing tests and bit-level tests can be performed in parallel. The bit-level tests and apparatus comprise iteratively measuring a coarse timestamp for a transition in the signal and comparing the measured coarse timestamp to an expected timestamp to determine whether the device meets specifications. Whether the device meets specifications depends on whether, during the comparison step, the presence of a bit-level fault is detected. The apparatus and method may comprise Skew Fault detection, Bit Fault detection, No Coverage Warning detection and/or Drift Fault detection. An automatic testing system for testing devices comprises subsystems that incorporate the apparatus and method.

Abstract: The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said digital clocks from said reference clock using a clock multiplier, respectively, resetting said clock multiplier in response to said synchronizing signal, and masking an output signal of said clock multiplier during settling time of said clock multiplier.

Abstract: A method and system for synthesizing digital clock signals for an electronic device under test having a plurality of pins, said method including generating centrally a reference clock, and distributing said reference clock to a number of electronic circuits, each of said electronic circuit having a test signal processor controlling electrically said pins of said device under test with predetermined signal pattern, characterized by synthesizing locally at said test signal processor a digital clock signal, said digital clock signal being individual for said pin of said device under test electrically controlled by said test signal processor.

Abstract: The present invention relates to a method for providing an improved generated arbitrary waveform using a sigma-delta modulator with pulse width modulation, said method comprising the steps of sigma-delta modulation of said generated arbitrary waveform, and pulse width modulation of the output signal of said sigma-delta modulator, introducing a minimum pulse width (pwmin) during said pulse width modulation.

Abstract: Using component-level test data to reduce system test. By modeling a system, sensitivity analysis reveals critical components and parameters of those components required to meet system performance parameters. Critical components are tested for these parameters, and these measurements associated with the components. Systems may be assembled which are modeled to meet the system performance parameters based on the model and the measured parameters. Systems may be assembled and calibration coefficients derived and applied from the model and the measured parameters.

Abstract: The present invention relates to a method for tracking transitions in a bit stream of a signal, said method comprising the steps of taking a first sample of said bit stream at a first sampling point of a first sampling sequence, taking a second sample of said bit stream at a second sampling point of said first sampling sequence, and taking a third sample of said bit stream at a third sampling point of said first sampling sequence, wherein said second sampling point is adjusted so that within a first time period, defined by said first and said second sampling points, the number of transitions in said bit stream is equal to the number of transitions within a second time period, defined by said second and said third sampling points.