Patents by Inventor Jochen Thomas

Jochen Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10035680
    Abstract: An elevator safety circuit includes a plurality of relays; safety logic for monitoring status of the plurality of relays, the safety logic generating an output signal in response to the status of the plurality of relays; and a processor controlling operation of an elevator drive in response to the output signal; wherein at least one of the relays is a forced guided relay and at least one of the relays is other than a forced guided relay.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: July 31, 2018
    Assignee: OTIS ELEVATOR COMPANY
    Inventors: Jochen Thomas Richter, Hebert Horbr├╝gger, Richard F. Magda, Marvin Dehmlow
  • Publication number: 20160002005
    Abstract: An elevator safety circuit includes a plurality of relays; safety logic for monitoring status of the plurality of relays, the safety logic generating an output signal in response to the status of the plurality of relays; and a processor controlling operation of an elevator drive in response to the output signal; wherein at least one of the relays is a forced guided relay and at least one of the relays is other than a forced guided relay.
    Type: Application
    Filed: February 14, 2013
    Publication date: January 7, 2016
    Inventors: Jochen Thomas Richter, Hebert Horbr├╝gger, Richard F. Magda, Marvin Dehmlow
  • Patent number: 8624372
    Abstract: A semiconductor component (10) has an interposer substrate (1) as stack element of a semiconductor component stack (25). The interposer substrate (1) has, on one of the interposer substrate sides (2, 4), a semiconductor chip protected by plastics composition (12) in its side edges (22). An interposer structure (3) partly covered by a plastics composition (12) is arranged on the interposer side (2, 4) opposite to the semiconductor chip (6). Edge regions (11) of the interposer substrate (1) remain free of any plastics composition (12) and have, on both interposer sides (2, 4) external contact pads (7) which are electrically connected to one another via through contacts (8).
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: January 7, 2014
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Hetzel, Jochen Thomas, Peter Weitz, Ingo Wennemuth
  • Patent number: 8072085
    Abstract: A semiconductor device with a plastic package molding compound, a semiconductor chip and a leadframe is disclosed. In one embodiment, the semiconductor chip is embedded in a plastic package molding compound. The upper side of the semiconductor chip and the plastic package molding compound are arranged on a leadframe. Arranged between the leadframe and the plastic package molding compound with the semiconductor chip is an elastic adhesive layer for the mechanical decoupling of an upper region from a lower region of the semiconductor device.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: December 6, 2011
    Assignee: Qimonda AG
    Inventors: Wolfgang Hetzel, Jochen Thomas
  • Patent number: 7948071
    Abstract: An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: May 24, 2011
    Assignee: Qimonda AG
    Inventors: Jochen Thomas, Peter Weitz, Jurgen Grafe, Harry Hedler, Jens Pohl
  • Patent number: 7851899
    Abstract: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: December 14, 2010
    Assignees: UTAC - United Test and Assembly Test Center Ltd., Infineon Technologies
    Inventors: Fung Leng Chen, Seong Kwang Brandon Kim, Wee Lim Cha, Yi-Sheng Anthony Sun, Wolfgang Hetzel, Jochen Thomas
  • Publication number: 20100032817
    Abstract: A semiconductor device with a plastic package molding compound, a semiconductor chip and a leadframe is disclosed. In one embodiment, the semiconductor chip is embedded in a plastic package molding compound. The upper side of the semiconductor chip and the plastic package molding compound are arranged on a leadframe. Arranged between the leadframe and the plastic package molding compound with the semiconductor chip is an elastic adhesive layer for the mechanical decoupling of an upper region from a lower region of the semiconductor device.
    Type: Application
    Filed: October 25, 2004
    Publication date: February 11, 2010
    Inventors: Wolfgang Hetzel, Jochen Thomas
  • Patent number: 7456505
    Abstract: Embodiments provide for integrated circuit chip and device having such an integrated circuit, in which different types of pads are arranged in separate rows. In one embodiment the pads are arranged to reduce the loop inductance of corresponding signal and power supply bond wires.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: November 25, 2008
    Assignee: Infineon Technologies AG
    Inventors: Minka Gospodinova, Jochen Thomas, Dominique Savignac
  • Patent number: 7422930
    Abstract: An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: September 9, 2008
    Assignee: Infineon Technologies AG
    Inventors: Jochen Thomas, Peter Weitz, Jurgen Grafe, Harry Hedler, Jens Pohl
  • Publication number: 20080203575
    Abstract: An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die.
    Type: Application
    Filed: May 6, 2008
    Publication date: August 28, 2008
    Inventors: Jochen Thomas, Peter Weitz, Jurgen Grafe, Harry Hedler, Jens Pohl
  • Publication number: 20080203581
    Abstract: An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first interface layer on a first substrate, the first interface layer including a first signal path, a second interface layer on the first interface layer, the second interface layer including a second signal path, the second signal path being coupled to the first signal path, and a second substrate on the second interface layer. In one embodiment, the second substrate includes an electronic device, the electronic device being coupled to the second signal path of the second interface layer.
    Type: Application
    Filed: February 27, 2007
    Publication date: August 28, 2008
    Applicant: QIMONDA AG
    Inventors: Jochen Thomas, Wolfgang Hetzel, Mathias Grumm
  • Patent number: 7402911
    Abstract: The present invention relates to a multi-chip device comprising a substrate having a first surface on which a number of first contact elements is provided, a plurality of integrated circuit chips arranged in a chip stack which is arranged on a second surface of the substrate opposing the first surface, wherein each of the chips having a surface on which a number of second contact elements are provided, wherein a first one of the chips and the second contact elements thereon is arranged such that its second contact elements are uncovered by any of the chips or by the substrate and face towards the second surface of the substrate; and connecting elements which are arranged such as to connect at least one of the first contact elements of the substrate and at least one of the second contact elements of the first chip.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: July 22, 2008
    Assignee: Infineon Technologies AG
    Inventors: Jochen Thomas, Wolfgang Hetzel
  • Publication number: 20080079150
    Abstract: Die arrangement, having a die with a plurality of electronic circuits electrically coupled to one another, at least one first electrical connection region, having at least one electrical connection, and a first passivation layer, which is applied whilst leaving free at least the one first electrical connection region. A second passivation layer, preferably a molding material, is arranged at least partly on the first passivation layer. At least one electrically conductive structure with a connecting element and a redistribution layer electrically connects the first electrical connection to a second electrical connection, which is formed by or at a section of the redistribution layer. The connecting element extends from the first electrical connection region through the first passivation layer and the second passivation layer, the redistribution layer coupled to the connecting section being arranged at least partly on the second passivation layer.
    Type: Application
    Filed: September 28, 2006
    Publication date: April 3, 2008
    Inventors: Juergen Simon, Laurence Edward Singleton, Jochen Thomas
  • Patent number: 7352057
    Abstract: A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: April 1, 2008
    Assignee: Infineon Technologies AG
    Inventors: Jurgen Grafe, Sylke Ludewig, Jochen Thomas, Peter Weitz
  • Patent number: 7345363
    Abstract: A semiconductor device includes a plastic package, at least one semiconductor chip and a rewiring level. The rewiring level includes an insulating layer and a rewiring layer. The rewiring layer includes either signal conductor paths and ground or supply conductor paths arranged parallel to one another and alternately, or only signal conductor paths arranged parallel to one another. In the latter case, an electrically conducting layer of metal which can be connected to ground or supply potential is additionally provided as a termination of the rewiring level or in the form of a covering layer.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: March 18, 2008
    Assignee: Infineon Technologies AG
    Inventors: Minka Gospodinova-Daltcheva, Harry Huebert, Rajesh Subraya, Jochen Thomas, Ingo Wennemuth
  • Patent number: 7297574
    Abstract: The present invention relates to a multi-chip device comprising a plurality of chip stacks each including a plurality of single chips stacked on each other, wherein the stacked single chips are electrically interconnected by one or more through-chip-connection extending through at least one of the single chips and a substrate providing one or more first contact elements each of which is in contact with one of the through-chip-connections and providing one or more second contact elements being in electrical contact with the first contact elements, wherein the plurality of chip stacks are stacked onto each other and wherein the second contact elements of one of the chip stacks each being arranged to be in contact to one or more third contact elements of an adjacent one of the chip stacks.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: November 20, 2007
    Assignee: Infineon Technologies AG
    Inventors: Jochen Thomas, Olaf Schoenfeld
  • Patent number: 7294910
    Abstract: The invention relates to an electronic component having a multilayered rewiring plate, which carries a circuit chip, in particular a magnetic memory chip, and connects contact areas of the chip to external contacts of the electronic component via rewiring lines. The rewiring plate has at least one patterned, magnetic shielding layer made of an amorphous metal or an amorphous metal alloy. Furthermore, the invention encompasses a method for producing this electronic component.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: November 13, 2007
    Assignee: Infineon Technologies AG
    Inventors: Jochen Thomas, Ingo Wennemuth
  • Publication number: 20070210433
    Abstract: The invention provides an integrated device comprising a plurality of non-individually-encapsulated chip arrangements, each of which having a plurality of contact elements for contacting a contact pad, wherein the plurality of chip arrangements are stacked on each other such that the respective contact elements provide electrical connections to the respective chip arrangement, and a common integral mold arranged to encapsulate the plurality of stacked chip arrangements.
    Type: Application
    Filed: March 8, 2006
    Publication date: September 13, 2007
    Inventors: Rajesh Subraya, Helmut Fischer, Ingo Wennemuth, Minka Gospodinova, Jochen Thomas
  • Patent number: 7253514
    Abstract: A connecting element for electrically connecting a semiconductor chip and a superordinate circuit board includes an elastic metal strip that is bent forming two metal limbs with flattened limb ends, thus forming a base between the metal limbs which is suitable for contacting and providing electrical connectivity to a plurality of contact pads of a superordinate circuit board. At least one of the two limb ends is electrically connected to the contact areas of a semiconductor chip, while the other limb end is elastically supported on the top side of the semiconductor chip, thereby enabling the connecting element to be self supporting.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: August 7, 2007
    Assignee: Infineon Technologies, AG
    Inventors: Anton Legen, Jochen Thomas, Ingo Wennemuth
  • Publication number: 20070158815
    Abstract: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.
    Type: Application
    Filed: April 2, 2004
    Publication date: July 12, 2007
    Inventors: Fung Chen, Seong Kwang Kim, Wee Cha, Yi-Sheng Sun, Wolfgang Hetzel, Jochen Thomas