Patents by Inventor Jody Fronheiser
Jody Fronheiser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240136229Abstract: A method of forming a multi-layer semiconductor device on a substrate includes forming a superlattice of a plurality of alternating first layers composed of a first material and second layers formed of a second material, removing the second layers of the superlattice, etching the first material layers to form trimmed first layers therefrom, wherein the quantity of material removed from different ones of the first layers are different amounts, forming a capping layer over the first layers, measuring at least one of the distance between the capping layers formed on the different ones of the first layers, the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers, and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover, and based on differences in the measurements, calculating a new thickness of the etched first layers.Type: ApplicationFiled: September 6, 2023Publication date: April 25, 2024Inventors: Jody FRONHEISER, Sai Hooi YEONG, Benjamin COLOMBEAU, Balasubramanian PRANATHARTHIHARAN, Lequn LIU
-
Publication number: 20240014214Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding material on a first material followed by a dry oxidation process resulting rearrangement of the cladding material and first material.Type: ApplicationFiled: July 10, 2023Publication date: January 11, 2024Applicant: Applied Materials, Inc.Inventors: Sai Hooi Yeong, Jody A. Fronheiser, Benjamin Colombeau, Balasubramanian Pranatharthiharan, El Mehdi Bazizi, Ashish Pal
-
Patent number: 10680065Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is arranged laterally between a first source/drain region and a second source/drain region. The channel region includes a first semiconductor layer and a second semiconductor layer arranged over the first semiconductor layer. A gate structure is arranged over the second semiconductor layer of the channel region The first semiconductor layer is composed of a first semiconductor material having a first carrier mobility. The second semiconductor layer is composed of a second semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer.Type: GrantFiled: August 1, 2018Date of Patent: June 9, 2020Inventors: George R. Mulfinger, Timothy J. McArdle, Jody Fronheiser, El Mehdi Bazizi, Yi Qi
-
Patent number: 10643893Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.Type: GrantFiled: June 29, 2016Date of Patent: May 5, 2020Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark V. Raymond, Tenko Yamashita
-
Patent number: 10643894Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.Type: GrantFiled: May 17, 2017Date of Patent: May 5, 2020Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark Raymond, Tenko Yamashita
-
Publication number: 20200044029Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is arranged laterally between a first source/drain region and a second source/drain region. The channel region includes a first semiconductor layer and a second semiconductor layer arranged over the first semiconductor layer. A gate structure is arranged over the second semiconductor layer of the channel region The first semiconductor layer is composed of a first semiconductor material having a first carrier mobility. The second semiconductor layer is composed of a second semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer.Type: ApplicationFiled: August 1, 2018Publication date: February 6, 2020Inventors: George R. Mulfinger, Timothy J. McArdle, Jody Fronheiser, El Mehdi Bazizi, Yi Qi
-
Patent number: 10170617Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.Type: GrantFiled: February 3, 2017Date of Patent: January 1, 2019Assignee: GLOBALFOUNDRIESInventors: Jiseok Kim, Hiroaki Niimi, Hoon Kim, Puneet Harischandra Suvarna, Steven Bentley, Jody A. Fronheiser
-
Patent number: 10170616Abstract: One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at the bottom of the cavity, and performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on the bottom source/drain (S/D) layer of semiconductor material and in the cavity and a top source/drain (S/D) layer of semiconductor material above the vertically oriented channel semiconductor structure. In this example, the method further includes removing at least one of the plurality of layers of material to thereby expose an outer perimeter surface of the vertically oriented channel semiconductor structure and forming a gate structure around the vertically oriented channel semiconductor structure.Type: GrantFiled: September 19, 2016Date of Patent: January 1, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Steven J. Bentley, Jody A. Fronheiser
-
Patent number: 10163677Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.Type: GrantFiled: December 20, 2017Date of Patent: December 25, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser
-
Publication number: 20180226505Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.Type: ApplicationFiled: February 3, 2017Publication date: August 9, 2018Inventors: Jiseok KIM, Hiroaki NIIMI, Hoon KIM, Puneet Harischandra SUVARNA, Steven BENTLEY, Jody A. FRONHEISER
-
Patent number: 10032912Abstract: A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.Type: GrantFiled: December 31, 2014Date of Patent: July 24, 2018Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pierre Morin, Kangguo Cheng, Jody Fronheiser, Xiuyu Cai, Juntao Li, Shogo Mochizuki, Ruilong Xie, Hong He, Nicolas Loubet
-
Methods of forming fin isolation regions under tensile-strained fins on FinFET semiconductor devices
Patent number: 10026659Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an NMOS FinFET device.Type: GrantFiled: January 29, 2015Date of Patent: July 17, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Jody A. Fronheiser -
Publication number: 20180138079Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.Type: ApplicationFiled: December 20, 2017Publication date: May 17, 2018Inventors: Murat Kerem AKARVARDAR, Jody A. FRONHEISER
-
Publication number: 20180130656Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.Type: ApplicationFiled: December 15, 2017Publication date: May 10, 2018Inventors: Judson Robert Holt, Jinping Liu, Jody Fronheiser, Bharat Krishnan, Churamani Gaire, Timothy James Mcardle, Murat Kerem Akarvardar
-
Patent number: 9960257Abstract: Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.Type: GrantFiled: March 12, 2015Date of Patent: May 1, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser, Ajey Poovannummoottil Jacob
-
Publication number: 20180083136Abstract: One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at the bottom of the cavity, and performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on the bottom source/drain (S/D) layer of semiconductor material and in the cavity and a top source/drain (S/D) layer of semiconductor material above the vertically oriented channel semiconductor structure. In this example, the method further includes removing at least one of the plurality of layers of material to thereby expose an outer perimeter surface of the vertically oriented channel semiconductor structure and forming a gate structure around the vertically oriented channel semiconductor structure.Type: ApplicationFiled: September 19, 2016Publication date: March 22, 2018Inventors: Ruilong Xie, Steven J. Bentley, Jody A. Fronheiser
-
Patent number: 9881830Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.Type: GrantFiled: January 6, 2015Date of Patent: January 30, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser
-
Patent number: 9882052Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.Type: GrantFiled: June 30, 2016Date of Patent: January 30, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Robert Judson Holt, Jinping Liu, Jody Fronheiser, Bharat Krishnan, Churamani Gaire, Timothy James McArdle, Murat Kerem Akarvardar
-
Publication number: 20180006141Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.Type: ApplicationFiled: May 17, 2017Publication date: January 4, 2018Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark Raymond, Tenko Yamashita
-
Publication number: 20180006140Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark Raymond, Tenko Yamashita