Abstract: One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a <100> crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the substrate fin, wherein the replacement fin structure is comprised of a semiconductor material that is different from the first semiconductor material, and a gate structure positioned around at least a portion of the replacement fin structure.

Abstract: Methods are provided for fabricating integrated circuits. In accordance with one embodiment, the method includes forming a portion of a semiconductor substrate at least partially bounded by a confinement isolation material. A liner dielectric is formed overlying the confinement isolation material and is treated to passivate a surface thereof. An epitaxial layer of semiconductor material is then grown overlying the portion of semiconductor substrate.

Abstract: Methods are provided for fabricating integrated circuits. In accordance with one embodiment, the method includes forming a portion of a semiconductor substrate at least partially bounded by a confinement isolation material. A liner dielectric is formed overlying the confinement isolation material and is treated to passivate a surface thereof An epitaxial layer of semiconductor material is then grown overlying the portion of semiconductor substrate.

Abstract: One method herein includes forming a plurality of spaced-apart trenches that extend at least partially into a semiconducting substrate, wherein the trenches define a fin structure comprised of first and second layers of semiconducting material, wherein the first layer of semiconducting material is selectively etchable relative to the substrate and the second layer of semiconducting material, forming a sacrificial gate structure above the fin, wherein the gate structure includes a gate insulation layer and a gate electrode, forming a sidewall spacer adjacent the gate structure, performing an etching process to remove the sacrificial gate structure, thereby defining a gate cavity, performing at least one selective etching process to selectively remove the first layer of semiconducting material relative to the second layer of semiconducting material within the gate cavity, thereby defining a space between the second semiconducting material and the substrate, and forming a final gate structure in the gate cavity.

Abstract: One method involves providing a substrate comprised of first and second semiconductor materials, performing an etching process through a hard mask layer to define a plurality of trenches that define first and second portions of a fin for a FinFET device, wherein the first portion is the first material and the second portion is the second material, forming a layer of insulating material in the trenches, performing a planarization process on the insulating material, performing etching processes to remove the hard mask layer and reduce a thickness of the second portion, thereby defining a cavity, performing a deposition process to form a third portion of the fin on the second portion, wherein the third portion is a third semiconducting material that is different from the second material, and performing a process such that a post-etch upper surface of the insulating material is below an upper surface of the third portion.

Abstract: One method involves providing a substrate comprised of first and second semiconductor materials, performing an etching process through a hard mask layer to define a plurality of trenches that define first and second portions of a fin for a FinFET device, wherein the first portion is the first material and the second portion is the second material, forming a layer of insulating material in the trenches, performing a planarization process on the insulating material, performing etching processes to remove the hard mask layer and reduce a thickness of the second portion, thereby defining a cavity, performing a deposition process to form a third portion of the fin on the second portion, wherein the third portion is a third semiconducting material that is different from the second material, and performing a process such that a post-etch upper surface of the insulating material is below an upper surface of the third portion.

Abstract: One illustrative method disclosed herein involves performing a first etching process through a patterned hard mask layer to define a plurality of spaced-apart trenches in a substrate that defines a first portion of a fin for the device, forming a layer of insulating material in the trenches and performing a planarization process on the layer of insulating material to expose the patterned hard, performing a second etching process to remove the hard mask layer and to define a cavity within the layer of insulating material, forming a second portion of the fin within the cavity, wherein the second portion of the fin is comprised of a semiconducting material that is different than the substrate, and performing a third etching process on the layer of insulating material such that an upper surface of the insulating material is below an upper surface of the second portion of the fin.

Abstract: One illustrative method disclosed herein involves performing a first etching process through a patterned hard mask layer to define a plurality of spaced-apart trenches in a substrate that defines a first portion of a fin for the device, forming a layer of insulating material in the trenches and performing a planarization process on the layer of insulating material to expose the patterned hard, performing a second etching process to remove the hard mask layer and to define a cavity within the layer of insulating material, forming a second portion of the fin within the cavity, wherein the second portion of the fin is comprised of a semiconducting material that is different than the substrate, and performing a third etching process on the layer of insulating material such that an upper surface of the insulating material is below an upper surface of the second portion of the fin.

Abstract: A method for forming an array of elongated nanostructures, includes in one embodiment, providing a substrate, providing a template having a plurality of pores on the substrate, and removing portions of the substrate under the plurality of pores of the template to form a plurality of cavities. A catalyst is provided in the plurality of cavities in the substrate, and the pores of the template are widened to expose the substrate around the catalyst so that the catalyst is spaced from the sides of the plurality of pores of the template. A plurality of elongated nanostructures is grown from the catalyst spaced from the sides of the pores of the template.

Abstract: Disclosed herein is a nanodevice. Disclosed herein too is a method of manufacturing a nanodevice. In one embodiment the nanodevice includes a first substrate; a second substrate; a nanowire; the nanowire contacting the first substrate and the second substrate; the nanowire comprising a metal, a semi-conductor or a combination thereof.

Abstract: A method for forming an array of elongated nanostructures, includes in one embodiment, providing a substrate, providing a template having a plurality of pores on the substrate, and removing portions of the substrate under the plurality of pores of the template to form a plurality of cavities. A catalyst is provided in the plurality of cavities in the substrate, and the pores of the template are widened to expose the substrate around the catalyst so that the catalyst is spaced from the sides of the plurality of pores of the template. A plurality of elongated nanostructures is grown from the catalyst spaced from the sides of the pores of the template.

Abstract: A power device includes at least one n-type semiconductor layer and at least one p-type silicon carbide epitaxial layer comprising gallium acceptors. Another power device includes at least one epitaxial silicon carbide layer and at least one p-type region formed epitaxially in the epitaxial silicon carbide layer. The p-type region comprises gallium acceptors. A method for forming a semiconductor device includes forming a first conductivity type semiconductor layer on a substrate, forming a second conductivity type semiconductor layer on the first conductivity type semiconductor layer. At least one of the semiconductor layers comprises silicon carbide, and one of the forming steps comprises epitaxially doping the respective silicon carbide layer with gallium acceptors.