Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

Abstract: Provided are a device and method for evaluating performance of a wearable muscle enhancement device.

Abstract: Herein is database query acceleration from dynamic discovery of whether contents of a persistent column can be stored in an accelerated representation in storage-side memory. In an embodiment, based on data type discovery, a storage server detects that column values in a persistent column have a particular data type. Based on storage-side metadata including a frequency of access of the persistent column as an offload input column for offload computation requests on a certain range of memory addresses, the storage server autonomously decides to generate and store, in storage-side memory in the storage server, an accelerated representation of the persistent column that is based on the particular data type. The storage server receives a request to perform an offload computation for the offload input column. Based on the accelerated representation of the persistent column, execution of the offload computation is accelerated.

Abstract: One embodiment of the present specification provides a siloxane compound represented by Chemical Formula 1 below: In Chemical Formula 1, R1a and R1b are each independently a substituted or unsubstituted straight or branched-chain alkyl group having 1 to 16 carbon atoms, R2a and R2b are each independently a substituted or unsubstituted straight or branched-chain alkyl group having 1 to 16 carbon atoms, R3a and R3b are each independently a substituted or unsubstituted straight or branched-chain alkylene group having 1 to 16 carbon atoms, R4a, R4b, R5a, and R5b are each independently hydrogen, a substituted or unsubstituted straight or branched alkyl group having 1 to 16 carbon atoms, or a substituted or unsubstituted straight or branched-chain heteroalkyl group having 1 to 16 carbon atoms, m1 and m2 are each an integer from 0 to 2, and when m1 and m2 are each 0, a plurality of OR2a and OR2b are the same or different, and when m1 and m2 are each 2, a plurality of R1a and R1b are the same or different, and x

Abstract: A method for producing a tandem sub for a perforating gun system includes positioning an electrically conductive signal bar in a central passage of a tubular housing of the tandem sub, and injecting a mold material into an annulus formed between an outer surface of the signal bar and an inner surface of the tubular housing that sealably adheres to both the signal bar and the tubular housing.

Abstract: A collapsible container having a base, an upper frame, and a pair of opposed side walls pivotably connected to side edges of the upper frame. Each of the side walls including an upper panel hingeably connected to a lower panel. The lower panel is hingeably connected to the base. A pair of opposed end walls are pivotably connected to end edges of the upper frame. The end walls are pivotable between an upright position extending from the upper frame to the base between the side walls and a retracted position within the upper frame. A lid is pivotably secured to the upper frame. Other embodiments are also disclosed.

Abstract: A method of forming a mandrel for use in a pitch doubling process is provided in which a metal hard mask is inserted between a mandrel material layer and a soft mask. The insertion of the metal hard mask allows for easier pattern transfer into the mandrel material layer and avoids many issues encountered during multi-patterning steps. The insertion of the metal hard mask forms a square mandrel that has a flat top due to durability against etch and ability to wet strip the metal hard mask. The metal hard mask can be tuned before pattern transfer into the underlying mandrel material layer to provide a hard mask pattern that is smaller or larger than the pattern without performing such tuning. The method also can be used to protect the downstream non-mandrel processes where selectivity is crucial.

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Abstract: Split ash processes are disclosed to suppress damage to low-dielectric-constant (low-K) layers during via formation. For one embodiment, ash processes used to remove an organic layer, such as an organic planarization layer (OPL), associated with via formation are split into multiple ash process steps that are separated by intervening process steps. A first ash process is performed to remove a portion of an organic layer after vias have been partially opened to a low-K layer. Subsequently, after the vias are fully opened through the low-K layer, an additional ash process is performed to remove the remaining organic material. Although some damage may still occur on via sidewalls due to this split ash processing, the damage is significantly reduced as compared to prior solutions, and device performance is improved. Target critical dimension (CD) for vias and effective dielectric constants for the low-K layer are achieved.

Abstract: A pallet includes a deck having center portion and two outer portions spaced outward on either side of the center portion. A plurality of keg supports extend from each outer portion to the center portion. Each keg support has a concave upper surface. A large opening is defined between each adjacent pair of keg supports. Outer middle recesses are formed on each outer portion adjacent each large opening. Center middle recesses are formed on the center portion adjacent each large opening. A plurality of column portions protrude from the deck. The pallet accommodates both straight kegs and belly kegs at the same height. The pallet may be formed in two identical halves.

Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

Abstract: Method and apparatus for a completion mechanism for a microprocessor are provided by identifying entries in a section of an Instruction Completion Table (ICT) that are marked as ready to complete via corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion; determining a head pointer that indicates an end of the entries in the ICT that are ready for completion; completing instructions included in the entries between the tail pointer and the head pointer; and updating the tail pointer to a value of the head pointer for a subsequent instruction completion round.

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Abstract: A pallet includes a deck having an opening therethrough, such that product can be removed through the opening from a box loaded on the deck of a pallet. A plurality of columns support the deck. The box may be supported on the deck over the opening. The bottom wall of the box may be opened though the opening in the deck. The items can then be removed from the box through the opening through the deck without removing the box from the pallet. Optionally, fasteners may secure flaps of the box in corners of the deck of a pallet. According to another feature, a brace having an elongated body portion can be secured to an opening of the pallet, such that the elongated body portion abuts goods that are supported on the deck.

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Abstract: Bottom barrier free interconnects are provided. In one aspect, an interconnect structure includes: metal lines embedded in a dielectric; an interlayer dielectric (ILD) disposed over the metal lines; interconnects formed in the ILD on top of the metal lines; a barrier layer separating the interconnects from the ILD, wherein the barrier layer is absent in between the interconnects and the metal lines; and a selective capping layer disposed on the interconnects.

Abstract: A first pallet includes a deck and a peripheral wall extending downward from a periphery of the deck. A plurality of feet extend downward from the deck. Each of the feet includes a foot wall defining its periphery. An outer portion of each foot wall is coterminous with the peripheral wall of the deck. The deck includes an opening aligned with each of the plurality of feet. A second, wider pallet may be used with the first pallet. The second pallet may be stacked on the first pallet and vice versa. In the second pallet, the outer portion of the wall of each of the feet is spaced inward from the peripheral wall of the deck, such that the deck of the second pallet is wider than the deck of the first pallet, but the spacing and size of the feet of both decks are identical.

Abstract: Techniques to enable bottom barrier free interconnects without voids. In one aspect, a method of forming interconnects includes: forming metal lines embedded in a dielectric; depositing a sacrificial dielectric over the metal lines; patterning vias and trenches in the sacrificial dielectric down to the metal lines, with the trenches positioned over the vias; lining the vias and trenches with a barrier layer; depositing a conductor into the vias and trenches over the barrier layer to form the interconnects; forming a selective capping layer on the interconnects; removing the sacrificial dielectric in its entirety; and depositing an interlayer dielectric (ILD) to replace the sacrificial dielectric. An interconnect structure is also provided.

Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

Abstract: A method is presented for forming interlayer connections in a semiconductor device. The method includes patterning an etch stack to provide for a plurality of interlayer connections, etching guide layers following the etch stack to a first capping layer to form a plurality of guide openings, concurrently exposing a first plurality of conductive lines and a second plurality of conductive lines to form a plurality of interlayer connection openings by etching through the plurality of guide openings to remove the first capping layer, an interlayer dielectric, and a second capping layer, and depositing a metal fill in the plurality of interlayer connection openings to form the plurality of interlayer connections.