Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

Abstract: A pallet includes a deck having center portion and two outer portions spaced outward on either side of the center portion. A plurality of keg supports extend from each outer portion to the center portion. Each keg support has a concave upper surface. A large opening is defined between each adjacent pair of keg supports. Outer middle recesses are formed on each outer portion adjacent each large opening. Center middle recesses are formed on the center portion adjacent each large opening. A plurality of column portions protrude from the deck. The pallet accommodates both straight kegs and belly kegs at the same height. The pallet may be formed in two identical halves.

Abstract: Bottom barrier free interconnects are provided. In one aspect, an interconnect structure includes: metal lines embedded in a dielectric; an interlayer dielectric (ILD) disposed over the metal lines; interconnects formed in the ILD on top of the metal lines; a barrier layer separating the interconnects from the ILD, wherein the barrier layer is absent in between the interconnects and the metal lines; and a selective capping layer disposed on the interconnects.

Abstract: A pallet includes a deck having center portion and two outer portions spaced outward on either side of the center portion. A plurality of keg supports extend from each outer portion to the center portion. Each keg support has a concave upper surface. A large opening is defined between each adjacent pair of keg supports. Outer middle recesses are formed on each outer portion adjacent each large opening. Center middle recesses are formed on the center portion adjacent each large opening. A plurality of column portions protrude from the deck. The pallet accommodates both straight kegs and belly kegs at the same height. The pallet may be formed in two identical halves.

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Abstract: A semiconductor device includes a semiconductor substrate including shallow trench isolation (STI) regions, a semiconductor fin between the STI regions, and a STI liner on an upper surface of the STI regions. A STI layer is in each of the STI regions, and includes a liner opening exposing a portion of the STI layer. A source/drain is on a sidewall of the semiconductor fin. A multi-stage backside contact is on the source/drain and contacting the portion of the STI layer via the liner opening.

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

Abstract: A collapsible container having a base, an upper frame, and a pair of opposed side walls pivotably connected to side edges of the upper frame. Each of the side walls including an upper panel hingeably connected to a lower panel. The lower panel is hingeably connected to the base. A pair of opposed end walls are pivotably connected to end edges of the upper frame. The end walls are pivotable between an upright position extending from the upper frame to the base between the side walls and a retracted position within the upper frame. A lid is pivotably secured to the upper frame. Other embodiments are also disclosed.

Abstract: A method of forming a mandrel for use in a pitch doubling process is provided in which a metal hard mask is inserted between a mandrel material layer and a soft mask. The insertion of the metal hard mask allows for easier pattern transfer into the mandrel material layer and avoids many issues encountered during multi-patterning steps. The insertion of the metal hard mask forms a square mandrel that has a flat top due to durability against etch and ability to wet strip the metal hard mask. The metal hard mask can be tuned before pattern transfer into the underlying mandrel material layer to provide a hard mask pattern that is smaller or larger than the pattern without performing such tuning. The method also can be used to protect the downstream non-mandrel processes where selectivity is crucial.

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Abstract: Split ash processes are disclosed to suppress damage to low-dielectric-constant (low-K) layers during via formation. For one embodiment, ash processes used to remove an organic layer, such as an organic planarization layer (OPL), associated with via formation are split into multiple ash process steps that are separated by intervening process steps. A first ash process is performed to remove a portion of an organic layer after vias have been partially opened to a low-K layer. Subsequently, after the vias are fully opened through the low-K layer, an additional ash process is performed to remove the remaining organic material. Although some damage may still occur on via sidewalls due to this split ash processing, the damage is significantly reduced as compared to prior solutions, and device performance is improved. Target critical dimension (CD) for vias and effective dielectric constants for the low-K layer are achieved.

Abstract: A pallet includes a deck having center portion and two outer portions spaced outward on either side of the center portion. A plurality of keg supports extend from each outer portion to the center portion. Each keg support has a concave upper surface. A large opening is defined between each adjacent pair of keg supports. Outer middle recesses are formed on each outer portion adjacent each large opening. Center middle recesses are formed on the center portion adjacent each large opening. A plurality of column portions protrude from the deck. The pallet accommodates both straight kegs and belly kegs at the same height. The pallet may be formed in two identical halves.

Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

Abstract: Method and apparatus for a completion mechanism for a microprocessor are provided by identifying entries in a section of an Instruction Completion Table (ICT) that are marked as ready to complete via corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion; determining a head pointer that indicates an end of the entries in the ICT that are ready for completion; completing instructions included in the entries between the tail pointer and the head pointer; and updating the tail pointer to a value of the head pointer for a subsequent instruction completion round.

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Abstract: A pallet includes a deck having an opening therethrough, such that product can be removed through the opening from a box loaded on the deck of a pallet. A plurality of columns support the deck. The box may be supported on the deck over the opening. The bottom wall of the box may be opened though the opening in the deck. The items can then be removed from the box through the opening through the deck without removing the box from the pallet. Optionally, fasteners may secure flaps of the box in corners of the deck of a pallet. According to another feature, a brace having an elongated body portion can be secured to an opening of the pallet, such that the elongated body portion abuts goods that are supported on the deck.

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.