Patents by Inventor Joe Margetis

Joe Margetis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240332016
    Abstract: A method of forming a silicon germanium layer on a surface of a substrate and a system for forming a silicon germanium layer are disclosed. Examples of the disclosure provide a method that includes providing a plurality of growth precursors to control and/or promote parasitic gas-phase and surface reactions, such that greater control of the film (e.g., thickness and/or composition) uniformity can be realized.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Inventors: Amir Kajbafvala, Peter Westrom, Joe Margetis, Xin Sun, Caleb Miskin, Yen Lin Leow, Yanfu Lu
  • Publication number: 20240274437
    Abstract: Methods and systems for forming structures including one or more layers comprising silicon germanium and one or more layers comprising silicon are disclosed. Exemplary methods can include using a surfactant, using particular precursors, and/or using a transition step to improve an interface between adjacent layers comprising silicon germanium and comprising silicon.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 15, 2024
    Inventors: Amir Kajbafvala, Joe Margetis, Xin Sun, David Kohen, Dieter Pierreux
  • Patent number: 12057314
    Abstract: A method of forming a silicon germanium layer on a surface of a substrate and a system for forming a silicon germanium layer are disclosed. Examples of the disclosure provide a method that includes providing a plurality of growth precursors to control and/or promote parasitic gas-phase and surface reactions, such that greater control of the film (e.g., thickness and/or composition) uniformity can be realized.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: August 6, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Amir Kajbafvala, Peter Westrom, Joe Margetis, Xin Sun, Caleb Miskin, Yen Lin Leow, Yanfu Lu
  • Patent number: 11996289
    Abstract: Methods and systems for forming structures including one or more layers comprising silicon germanium and one or more layers comprising silicon are disclosed. Exemplary methods can include using a surfactant, using particular precursors, and/or using a transition step to improve an interface between adjacent layers comprising silicon germanium and comprising silicon.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: May 28, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Amir Kajbafvala, Joe Margetis, Xin Sun, David Kohen, Dieter Pierreux
  • Publication number: 20230145240
    Abstract: A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 11, 2023
    Inventors: John Tolle, Joe Margetis, David Kohen
  • Publication number: 20230012819
    Abstract: Three-dimensional dynamic random-access memory (3D DRAM) structures and methods of formation of same are provided herein. In some embodiments, a 3D DRAM stack can include alternating silicon (Si) layers and silicon germanium (SiGe) layers. Each of the Si layers may have a height greater than a height of each of the SiGe layers. Methods and systems for formation of such structures are further provided.
    Type: Application
    Filed: July 8, 2022
    Publication date: January 19, 2023
    Inventors: John Byron Tolle, Tomohiko Kitajima, Thomas John Kirschenheiter, Patricia M. Liu, Zuoming Zhu, Joe Margetis, Fredrick David Fishburn, Abdul Wahab Mohammed, Gill Yong Lee
  • Patent number: 11557474
    Abstract: A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: January 17, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: John Tolle, Joe Margetis, David Kohen
  • Publication number: 20220310825
    Abstract: A method for depositing a Group IV semiconductor is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include, exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA metalorganic dopant precursor. The methods may further include depositing a Group IV semiconductor on a surface of the substrate. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.
    Type: Application
    Filed: June 14, 2022
    Publication date: September 29, 2022
    Inventors: Joe Margetis, John Tolle
  • Patent number: 11374112
    Abstract: A method for depositing a Group IV semiconductor is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include, exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA metalorganic dopant precursor. The methods may further include depositing a Group IV semiconductor on a surface of the substrate. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: June 28, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Joe Margetis, John Tolle
  • Publication number: 20210375622
    Abstract: Methods and devices for epitaxially growing boron- and gallium-doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.
    Type: Application
    Filed: May 21, 2021
    Publication date: December 2, 2021
    Inventors: Lucas Petersen Barbosa Lima, Joe Margetis, John Tolle, Rami Khazaka, Qi Xie
  • Publication number: 20210358741
    Abstract: A method of forming a silicon germanium layer on a surface of a substrate and a system for forming a silicon germanium layer are disclosed. Examples of the disclosure provide a method that includes providing a plurality of growth precursors to control and/or promote parasitic gas-phase and surface reactions, such that greater control of the film (e.g., thickness and/or composition) uniformity can be realized.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 18, 2021
    Inventors: Amir Kajbafvala, Peter Westrom, Joe Margetis, Xin Sun, Caleb Miskin, Yen Lin Leow, Yanfu Lu
  • Patent number: 11168395
    Abstract: A flange, flange assembly, and reactor system including the flange and flange assembly are disclosed. An exemplary flange assembly includes heated and cooled sections to independently control temperatures of sections of the flange. Methods of using the flange, flange assembly and reactor system are also disclosed.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: November 9, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Sonti Sreeram, John Tolle, Joe Margetis, Junwei Su
  • Publication number: 20210327704
    Abstract: Methods and systems for forming structures including one or more layers comprising silicon germanium and one or more layers comprising silicon are disclosed. Exemplary methods can include using a surfactant, using particular precursors, and/or using a transition step to improve an interface between adjacent layers comprising silicon germanium and comprising silicon.
    Type: Application
    Filed: January 5, 2021
    Publication date: October 21, 2021
    Inventors: Amir Kajbafvala, Joe Margetis, Xin Sun, David Kohen, Dieter Pierreux
  • Patent number: 11018002
    Abstract: A method for selectively depositing a Group IV semiconductor on a surface of a substrate is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The method may further include, exposing the substrate to at least one Group IV precursor, and exposing the substrate to at least one Group IIIA halide dopant precursor. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: May 25, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Joe Margetis, John Tolle
  • Patent number: 11004977
    Abstract: A method for depositing a Group IV semiconductor on a surface of a substrate is disclosed. The method may include: providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include: exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA dopant precursor; wherein the at least one Group IIIA dopant precursor comprises a borohydride, an organic borohydride, a halide, or an organohalide. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: May 11, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: John Tolle, Joe Margetis
  • Publication number: 20210035802
    Abstract: A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.
    Type: Application
    Filed: July 17, 2020
    Publication date: February 4, 2021
    Inventors: John Tolle, Joe Margetis, David Kohen
  • Publication number: 20200224309
    Abstract: A flange, flange assembly, and reactor system including the flange and flange assembly are disclosed. An exemplary flange assembly includes heated and cooled sections to independently control temperatures of sections of the flange. Methods of using the flange, flange assembly and reactor system are also disclosed.
    Type: Application
    Filed: March 11, 2020
    Publication date: July 16, 2020
    Inventors: Sonti Sreeram, John Tolle, Joe Margetis, Junwei Su
  • Patent number: 10685834
    Abstract: A method for forming a forming a silicon germanium tin (SiGeSn) layer is disclosed. The method may include, providing a substrate within a reaction chamber, exposing the substrate to a pre-deposition precursor pulse, which comprises tin tetrachloride (SnCl4), exposing the substrate to a deposition precursor gas mixture comprising a hydrogenated silicon source, germane (GeH4), and tin tetrachloride (SnCl4), and depositing the silicon germanium tin (SiGeSn) layer over a surface of the substrate. Semiconductor device structures including a silicon germanium tin (SiGeSn) layer formed by the methods of the disclosure are also provided.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: June 16, 2020
    Assignee: ASM IP Holdings B.V.
    Inventors: Nupur Bhargava, Joe Margetis, John Tolle
  • Patent number: 10612136
    Abstract: A flange, flange assembly, and reactor system including the flange and flange assembly are disclosed. An exemplary flange assembly includes heated and cooled sections to independently control temperatures of sections of the flange. Methods of using the flange, flange assembly and reactor system are also disclosed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 7, 2020
    Assignee: ASM IP HOLDING, B.V.
    Inventors: Sonti Sreeram, John Tolle, Joe Margetis, Junwei Su
  • Publication number: 20200083375
    Abstract: A method for depositing a Group IV semiconductor on a surface of a substrate is disclosed. The method may include: providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include: exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA dopant precursor; wherein the at least one Group IIIA dopant precursor comprises a borohydride, an organic borohydride, a halide, or an organohalide. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 12, 2020
    Inventors: John Tolle, Joe Margetis