Patents by Inventor Joe Margetis

Joe Margetis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200083375
    Abstract: A method for depositing a Group IV semiconductor on a surface of a substrate is disclosed. The method may include: providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include: exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA dopant precursor; wherein the at least one Group IIIA dopant precursor comprises a borohydride, an organic borohydride, a halide, or an organohalide. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 12, 2020
    Inventors: John Tolle, Joe Margetis
  • Patent number: 10541333
    Abstract: A method for depositing a Group IV semiconductor on a surface of a substrate is disclosed. The method may include: providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include: exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA dopant precursor; wherein the at least one Group IIIA dopant precursor comprises a borohydride, an organic borohydride, a halide, or an organohalide. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 21, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: John Tolle, Joe Margetis
  • Publication number: 20200002811
    Abstract: A flange, flange assembly, and reactor system including the flange and flange assembly are disclosed. An exemplary flange assembly includes heated and cooled sections to independently control temperatures of sections of the flange. Methods of using the flange, flange assembly and reactor system are also disclosed.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Sonti Sreeram, John Tolle, Joe Margetis, Junwei Su
  • Patent number: 10446393
    Abstract: A method for forming a silicon-containing epitaxial layer is disclosed. The method may include, heating a substrate to a temperature of less than approximately 950° C. and exposing the substrate to a first silicon source comprising a hydrogenated silicon source, a second silicon source, a dopant source, and a halogen source. The method may also include depositing a silicon-containing epitaxial layer wherein the dopant concentration within the silicon-containing epitaxial layer is greater than 3×1021 atoms per cubic centimeter.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: October 15, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Nupur Bhargava, John Tolle, Joe Margetis, Matthew Goodman, Robert Vyne
  • Patent number: 10388509
    Abstract: A process for forming a thick defect-free epitaxial layer is disclosed. The process may comprise forming a buffer layer and a sacrificial layer prior to forming the thick defect-free epitaxial layer. The sacrificial layer and the thick defect-free epitaxial layer may be formed of the same material and at the same process conditions.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 20, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Joe Margetis, John Tolle
  • Patent number: 10262859
    Abstract: A gas distribution system is disclosed in order to obtain better film uniformity on a substrate in a cross-flow reactor. The better film uniformity may be achieved by an asymmetric bias on individual injection ports of the gas distribution system. The gas distribution may allow for varied tunability of the film properties.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 16, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Joe Margetis, John Tolle, Gregory Bartlett, Nupur Bhargava
  • Publication number: 20190027584
    Abstract: A method for selectively depositing a Group IV semiconductor on a surface of a substrate is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The method may further include, exposing the substrate to at least one Group IV precursor, and exposing the substrate to at least one Group IIIA halide dopant precursor. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.
    Type: Application
    Filed: June 5, 2018
    Publication date: January 24, 2019
    Inventors: Joe Margetis, John Tolle
  • Publication number: 20190027583
    Abstract: A method for depositing a Group IV semiconductor is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include, exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA metalorganic dopant precursor. The methods may further include depositing a Group IV semiconductor on a surface of the substrate. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.
    Type: Application
    Filed: June 5, 2018
    Publication date: January 24, 2019
    Inventors: Joe Margetis, John Tolle
  • Publication number: 20190027605
    Abstract: A method for depositing a Group IV semiconductor on a surface of a substrate is disclosed. The method may include: providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include: exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA dopant precursor; wherein the at least one Group IIIA dopant precursor comprises a borohydride, an organic borohydride, a halide, or an organohalide. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.
    Type: Application
    Filed: May 21, 2018
    Publication date: January 24, 2019
    Inventors: John Tolle, Joe Margetis
  • Publication number: 20190013199
    Abstract: A method for forming a forming a silicon germanium tin (SiGeSn) layer is disclosed. The method may include, providing a substrate within a reaction chamber, exposing the substrate to a pre-deposition precursor pulse, which comprises tin tetrachloride (SnCl4), exposing the substrate to a deposition precursor gas mixture comprising a hydrogenated silicon source, germane (GeH4), and tin tetrachloride (SnCl4), and depositing the silicon germanium tin (SiGeSn) layer over a surface of the substrate. Semiconductor device structures including a silicon germanium tin (SiGeSn) layer formed by the methods of the disclosure are also provided.
    Type: Application
    Filed: May 21, 2018
    Publication date: January 10, 2019
    Inventors: Nupur Bhargava, Joe Margetis, John Tolle
  • Publication number: 20180323059
    Abstract: A method for forming a silicon-containing epitaxial layer is disclosed. The method may include, heating a substrate to a temperature of less than approximately 950° C. and exposing the substrate to a first silicon source comprising a hydrogenated silicon source, a second silicon source, a dopant source, and a halogen source. The method may also include depositing a silicon-containing epitaxial layer wherein the dopant concentration within the silicon-containing epitaxial layer is greater than 3×1021 atoms per cubic centimeter.
    Type: Application
    Filed: April 19, 2018
    Publication date: November 8, 2018
    Inventors: Nupur Bhargava, John Tolle, Joe Margetis, Matthew Goodman, Robert Vyne
  • Publication number: 20180151358
    Abstract: A gas distribution system is disclosed in order to obtain better film uniformity on a substrate in a cross-flow reactor. The better film uniformity may be achieved by an asymmetric bias on individual injection ports of the gas distribution system. The gas distribution may allow for varied tunability of the film properties.
    Type: Application
    Filed: January 5, 2018
    Publication date: May 31, 2018
    Inventors: Joe Margetis, John Tolle, Gregory Bartlett, Nupur Bhargava
  • Patent number: 9905420
    Abstract: Methods of forming silicon germanium tin (SixGe1-xSny) films are disclosed. Exemplary methods include growing films including silicon, germanium and tin in an epitaxial chemical vapor deposition reactor. Exemplary methods are suitable for high volume manufacturing. Also disclosed are structures and devices including silicon germanium tin films.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: February 27, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Joe Margetis, John Tolle
  • Patent number: 9892913
    Abstract: A gas distribution system is disclosed in order to obtain better film uniformity on a substrate in a cross-flow reactor. The better film uniformity may be achieved by an asymmetric bias on individual injection ports of the gas distribution system. The gas distribution may allow for varied tunability of the film properties.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: February 13, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Joe Margetis, John Tolle, Gregory Bartlett, Nupur Bhargava
  • Publication number: 20170372884
    Abstract: A process for forming a thick defect-free epitaxial layer is disclosed. The process may comprise forming a buffer layer and a sacrificial layer prior to forming the thick defect-free epitaxial layer. The sacrificial layer and the thick defect-free epitaxial layer may be formed of the same material and at the same process conditions.
    Type: Application
    Filed: June 19, 2017
    Publication date: December 28, 2017
    Inventors: Joe Margetis, John Tolle
  • Publication number: 20170278707
    Abstract: A gas distribution system is disclosed in order to obtain better film uniformity on a substrate in a cross-flow reactor. The better film uniformity may be achieved by an asymmetric bias on individual injection ports of the gas distribution system. The gas distribution may allow for varied tunability of the film properties.
    Type: Application
    Filed: March 6, 2017
    Publication date: September 28, 2017
    Inventors: Joe Margetis, John Tolle, Gregory Bartlett, Nupur Bhargava
  • Publication number: 20170154770
    Abstract: Methods of forming silicon germanium tin (SiGexGe1?xSny) films are disclosed. Exemplary methods include growing films including silicon, germanium and tin in an epitaxial chemical vapor deposition reactor. Exemplary methods are suitable for high volume manufacturing. Also disclosed are structures and devices including silicon germanium tin films.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 1, 2017
    Inventors: Joe Margetis, John Tolle
  • Patent number: 9647114
    Abstract: Methods of forming p-type doped germanium-tin layers, systems for forming the p-type doped germanium-tin layers, and structures including the p-type doped germanium-tin layers are disclosed. The p-type doped germanium-tin layers include an n-type dopant, which allows relatively high levels of tin and/or p-type dopant to be included into the p-type doped germanium-tin layers.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: May 9, 2017
    Assignee: ASM IP Holding B.V.
    Inventors: Joe Margetis, John Tolle
  • Publication number: 20170047446
    Abstract: Methods of forming p-type doped germanium-tin layers, systems for forming the p-type doped germanium-tin layers, and structures including the p-type doped germanium-tin layers are disclosed. The p-type doped germanium-tin layers include an n-type dopant, which allows relatively high levels of tin and/or p-type dopant to be included into the p-type doped germanium-tin layers.
    Type: Application
    Filed: August 14, 2015
    Publication date: February 16, 2017
    Inventors: Joe Margetis, John Tolle