Abstract: An implantable medical device is adapted to be implanted at an implantation site within the vasculature and is capable of being implanted at the implantation site within the vasculature at more than one position relative to the implantation site. This may include a relative axial position and/or a relative rotational position. The implantable medical device includes an expandable frame that is adapted to expand from a collapsed configuration for delivery to an expanded configuration for deployment, and one or more radiopaque markers disposed relative to the expandable frame such that fluoroscopic imaging of the implantable medical device during deployment provides an indication of a position of the implantable medical device relative to the implantation site. The implantable medical device may be a replacement cardiac valve such as a replacement aortic valve, for example.

Abstract: A computing system can implement a circuit verification tool to perform scaled sampling of parameter values in a foundry model describing parameter variations for a manufacturing process capable of fabricating an integrated circuit described in a circuit design. The computing system can simulate the circuit design with the scaled samples of the parameter values, and build a geometric model to describe a response of the circuit design to the scaled samples of the parameter values during the simulation. The geometric model can include one or more failure regions corresponding to geometric descriptions for failures of the circuit design to meet a specification during simulation with the scaled samples of the parameter values. The computing system can estimate a yield for an output of the integrated circuit described by the circuit design based on the failure regions in the geometric model.

Abstract: A computing system can implement a circuit verification tool to perform scaled sampling of parameter values in a foundry model describing parameter variations for a manufacturing process capable of fabricating an integrated circuit described in a circuit design. The computing system can simulate the circuit design with the scaled samples of the parameter values, and build a geometric model to describe a response of the circuit design to the scaled samples of the parameter values during the simulation. The geometric model can include one or more failure regions corresponding to geometric descriptions for failures of the circuit design to meet a specification during simulation with the scaled samples of the parameter values. The computing system can estimate a yield for an output of the integrated circuit described by the circuit design based on the failure regions in the geometric model.

Abstract: A computer-implemented method for quickly analyzing the effect of process, voltage, temperature, and other variations when the variation analysis or circuit structure can be hierarchically composed into nested loops. The method has two main steps: first, it hierarchically generates a set of points and inserts them into a flat list of tuples, where each tuple contains a point from each level in the looping hierarchy. Second, it efficiently identifies and simulates failing tuples with the assistance of modeling to order the tuples to simulate. By using the present method, a designer does not have to simulate the full ECD at each and every statistical process point or PVT corner, which can same considerable time or compute effort.

Abstract: The present disclosure is directed to a modular bicycle rack that includes at least a first hoop structure, a second hoop structure, a first connector plate, and a second connector plate. The first hoop structure is attached to the second hoop structure by each of the first and second connector plates. A bicycle rack that is capable of providing parking and locking surfaces for at least four bicycles may be provided using only two connected hoop structures. However, additional parking and locking surfaces may be provided simply by the further connection of additional hoop structures. Embodiments of the present disclosure are also directed to a set of components that is configured to be easily shipped, such as by a parcel carrier, and assembled to provide a bicycle rack.

Abstract: A method and system to estimate failure rates in designs. N Monte Carlo samples are drawn from the random distribution that describes process variation in the design. A subset of these samples is selected, and that subset of Ninit samples are simulated (with a circuit simulator) to measure a performance value for each sample. A model is constructed, using the values of the Ninit process points as training inputs, and the corresponding Ninit performance values as training outputs. The candidate Monte Carlo samples are from the N Monte Carlo samples that have not yet been simulated. Each candidate is simulated on the model to get predicted performance values, and the samples are ordered in ascending (or descending) order of the predicted performance values. Simulation of candidates samples is then begun, in that order. The sampling and simulation will stops once there is sufficient confidence that all failures are found.

Abstract: A computer-implemented method for quickly analyzing the effect of process, voltage, temperature, and other variations when the variation analysis or circuit structure can be hierarchically composed into nested loops. The method has two main steps: first, it hierarchically generates a set of points and inserts them into a flat list of tuples, where each tuple contains a point from each level in the looping hierarchy. Second, it efficiently identifies and simulates failing tuples with the assistance of modeling to order the tuples to simulate. By using the present method, a designer does not have to simulate the full ECD at each and every statistical process point or PVT corner, which can same considerable time or compute effort.

Abstract: The present disclosure is directed to a modular bicycle rack that includes at least a first hoop structure, a second hoop structure, a first connector plate, and a second connector plate. The first hoop structure is attached to the second hoop structure by each of the first and second connector plates. A bicycle rack that is capable of providing parking and locking surfaces for at least four bicycles may be provided using only two connected hoop structures. However, additional parking and locking surfaces may be provided simply by the further connection of additional hoop structures. Embodiments of the present disclosure are also directed to a set of components that is configured to be easily shipped, such as by a parcel carrier, and assembled to provide a bicycle rack.

Abstract: Current embodiment: A string trimmer rack apparatus of the type having a rigid shaft (13) of sufficient size for holding a commercial string trimmer with a trimmer shaft cradle (2) and trimmer hand grip cradle (15). The main shaft (13) is connected by a swivel point (9), to a vertical shaft (26) which joins to tractor mount for attaching to a commercial zero-turn mower's frame. A foot control (12) allows operation of flotation, or pitch of string trimmer's string head and bumping of string trimmer's string head against a hard surface, or the ground to feed more trimmer line. Other embodiments are described and shown.

Abstract: A method for finding the process, voltage, temperature, parasitics, and power settings (PVTPP) corner at which an electrical circuit design has the worst-case optimum simulated output performance. The method uses a global optimization process in a series of iterations that aim to uncover the PVTPP corner at which the ECD has the worst-case output value. By using the present method, a designer does not have to simulate the ECD at each and every PVTPP corner, which can same considerable time or compute effort. Examples using Model-Building Optimization are provided.

Abstract: A system and method to analyze analog, mixed-signal, and custom digital circuits. The system and method displays to a user characteristic values of a circuit and statistical uncertainty values of the characteristic values early in a sampling or characterization run of the circuit. The characteristic values and their statistical uncertainties are updated as the sampling or characterization run progresses. The user can halt the sampling or characterization run once a desired level of uncertainty is attained. The system can automatically halt the sampling or characterization run, once the statistical uncertainty lie within a pre-determined range.

Abstract: A method and system to estimate failure rates in designs. N Monte Carlo samples are drawn from the random distribution that describes process variation in the design. A subset of these samples is selected, and that subset of Ninit samples are simulated (with a circuit simulator) to measure a performance value for each sample. A model is constructed, using the values of the Ninit process points as training inputs, and the corresponding Ninit performance values as training outputs. The candidate Monte Carlo samples are from the N Monte Carlo samples that have not yet been simulated. Each candidate is simulated on the model to get predicted performance values, and the samples are ordered in ascending (or descending) order of the predicted performance values. Simulation of candidates samples is then begun, in that order. The sampling and simulation will stops once there is sufficient confidence that all failures are found.

Abstract: A method for proximity-aware circuit design where a set of layout constraint values that satisfy predetermined performance or yield goals is determined in accordance with a layout effect model. One of the layout constraint values is then selected as a constraint input to layout design, and a design layout is performed with the selected layout constraint value to provide a semiconductor circuit design for the semiconductor circuit. The set of layout constraint values can be determined by varying an instance parameter of the layout effect model to determine a set of instance parameters that satisfy the at least one predetermined performance or yield goal in accordance with the layout effect model, and determining layout constraints associated with each instance parameter of the set of instance parameters, thus providing a number of candidates in a design space that can be evaluated according to performance and/or yield tradeoffs.

Abstract: For application to analog, mixed-signal, and custom digital circuits, a system and method to begin with a complex problem description that encompasses many variables from statistical manufacturing, the circuit's environment, and the circuit's design parameters, but then apply techniques to prune the scope of the problem to make it manageable for manual design and more efficient automated design, and finally use that pruned problem for more efficient and effective design.

Abstract: For application to analog, mixed-signal, and custom digital circuits, a system and method to do: global statistical optimization (GSO), global statistical characterization (GSC), global statistical design (GSD), and block-specific design. GSO can perform global yield optimization on hundreds of variables, with no simplifying assumptions. GSC can capture and display mappings from design variables to performance, across the whole design space. GSC can handle hundreds of design variables in a reasonable time frame, e.g., in less than a day, for a reasonable number of simulations, e.g., less than 100,000. GSC can capture design variable interactions and other possible nonlinearities, explicitly capture uncertainties, and intuitively display them. GSD can support the user's exploration of design-to-performance mappings with fast feedback, thoroughly capturing design variable interactions in the whole space, and allow for more efficiently created, more optimal designs.

Abstract: A method for proximity-aware circuit design where a set of layout constraint values that satisfy predetermined performance or yield goals is determined in accordance with a layout effect model. One of the layout constraint values is then selected as a constraint input to layout design, and a design layout is performed with the selected layout constraint value to provide a semiconductor circuit design for the semiconductor circuit. The set of layout constraint values can be determined by varying an instance parameter of the layout effect model to determine a set of instance parameters that satisfy the at least one predetermined performance or yield goal in accordance with the layout effect model, and determining layout constraints associated with each instance parameter of the set of instance parameters, thus providing a number of candidates in a design space that can be evaluated according to performance and/or yield tradeoffs.

Abstract: The present invention features compounds of Formula (I) and (Ia), pharmaceutical compositions and use in the treatment of viral disease:

Abstract: For application to analog, mixed-signal, and custom digital circuits, a system and method to improve the flow of setting up a set of simulations, a characterization, or optimization problem via an interactive circuit schematic. A system and method to visualize circuit simulation data in which at least one of the views is an enhanced, interactive schematic view.

Abstract: Devices and methods for altering gaseous flow within a lung to improve the expiration cycle of an individual, particularly individuals having chronic obstructive pulmonary disease. The methods and devices create channels in lung tissue and maintain the patency of these surgically created channels in tissue. Maintaining the patency of the channels allows air to pass directly out of the lung tissue which facilitates the exchange of oxygen ultimately into the blood and/or decompresses hyper-inflated lungs.

Abstract: A system and method of generating a set of circuit simulation data, applying data mining to for knowledge extraction from the data, and graphically presenting the extracted knowledge in a format that is easy to digest to a designer.