Abstract: A layered flame retardant system and method is disclosed comprising a first flame retardant stable layer for covering a solid combustible material and a second moisture protecting polyolefin stretch film layer. The polyolefin stretch film layer further compactly affixes the first flame retardant stable layer to the solid combustible material. Some embodiments incorporate a five layer flame retardant polyolefin stretch film with flame retardant additives primarily in the inner layers. Another embodiment incorporates thermal insulating material.

Abstract: A Microwave/Millimeter-wave Monolithic Integrated Circuit (MMIC) device including PIN diode and Schottky diode circuits that provides improved performance with a reduced cost of manufacture. The planar, glass-passivated, MMIC device is fabricated in silicon technology and includes mesa isolation between the PIN diode and the Schottky diode. The PIN and Schottky diodes include respective anode regions having different thicknesses and resistivity for implementing the PIN and Schottky diode functions. Further, the Schottky anode region is formed relatively late in a process for fabricating the Si MMIC device to allow the Schottky anode region to be formed in approximately the same plane as the PIN anode region and to allow precise control of the relative thicknesses of the PIN and Schottky anode regions.

Abstract: A method of fabricating a hyperabrupt junction varactor diode structure comprises the steps of forming a non-uniformly doped n-type, hyperabrupt cathode region in a layer of semiconductor material and depositing, by ultra high vacuum chemical vapor deposition (UHVCVD), a p-type anode region onto a surface of the hyperabrupt cathode region. The deposition process is performed at relatively low temperature (i.e., below 600° C.). The anode region and the hyperabrupt cathode are joined at a junction between them such that an impurity concentration level of the hyperabrupt region increases in a direction toward the junction. During the forming step, n-type impurity ions are implanted at an implantation energy level substantially less than 300 keV, preferably between from about 10 to about 70 keV, with the implanted ions being thermally activated at a relatively low temperature (between from about 700 to about 800° C.).

Abstract: An outwardly grown diffusion aluminide bondcoat is formed on a superalloy substrate and has higher concentrations of Al and Pt and lower concentrations of harmful impurities (e.g. Mo, W, Cr, Ta, S, etc.) at an outermost region of the bondcoat than at an innermost region thereof adjacent the substrate. The bondcoat is pretreated prior to deposition of a ceramic thermal insulative layer in a manner that reduces grain boundary ridges on the outermost bondcoat surface without adversely affecting the outermost region thereof, and then is heat treated to thermally grow a stable alpha alumina layer on the bondcoat prior to deposition of a ceramic layer.

Abstract: An outwardly grown diffusion aluminide bondcoat is formed on a superalloy substrate and has higher concentrations of Al and Pt and lower concentrations of harmful impurities (e.g. Mo, W, Cr, Ta, S, etc.) at an outermost region of the bondcoat than at an innermost region thereof adjacent the substrate. The bondcoat is pretreated prior to deposition of a ceramic thermal insulative layer in a manner that reduces grain boundary ridges on the outermost bondcoat surface without adversely affecting the outermost region thereof, and then is heat treated to thermally grow a stable alpha alumina layer on the bondcoat prior to deposition of a ceramic layer.

Abstract: A process for fabricating heterolithic microwave integrated circuits. According to one exemplary embodiment, a glass substrate is fused to a silicon wafer, and the silicon wafer is etched to effect silicon pedestals. A glass layer is fused onto and about the silicon mesas and effectively polished to expose the tops of the silicon mesas. The backside glass layer is then polished to render a final thickness of the dielectric layer between the top surface and ground plane. In another exemplary embodiment, a layer of silicon may be selectively etched to form mesas that function as either pedestals or vias. A layer of glass may be fused to the silicon prior to etching. A layer of glass is fused to the silicon substrate and pedestals and planarized through standard polishing techniques. The wafer may be "flipped over" and polished in order to remove a substantial portion of the silicon or glass, depending on which is used. Thereafter, the integrated circuit is fabricated through standard techniques.

Abstract: Silicon conductive vias and pedestals are disclosed for use in microwave integrated circuits. The pedestals are isolated from a ground plane on the bottom surface by glass, while the vias are used to make electrical contact to ground. Electrical circuit elements in the top surface of the integrated circuit are selectively grounded or isolated by the choice of connection to a via or pedestal, respectively.

Abstract: A device works as an emergency shut off for a valve having an open and a closed position with a lever for manually moving the valve from one of the positions to the other.