Patents by Inventor Joel Turchi
Joel Turchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130322130Abstract: In one embodiment, a power supply controller is configured to adjust a peak value of a primary current through a power switch responsively to a difference between a demagnetization time and a discharge time of the parasitic leakage inductance of a transformer.Type: ApplicationFiled: June 5, 2012Publication date: December 5, 2013Inventor: Joel Turchi
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Publication number: 20120039007Abstract: A method and circuit for protecting against an over current condition. A conduction time of one or more transistors is reduced during the over current condition. The conduction time is reduced in an amount that is an increasing function of the amount of the over current. The conduction time may be reduced proportionally to the excess current.Type: ApplicationFiled: April 28, 2009Publication date: February 16, 2012Inventors: Joel Turchi, Stéphanie Conseil, Radim Mlcousek
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Publication number: 20120032695Abstract: A circuit and method for detecting a brown-out condition and providing a feed-forward transfer function in a power supply circuit. A comparison circuit is coupled to a delay element through a latch. A second delay element is connected between the first delay element and an input of the latch. The output of the first delay element is connected to a clamping circuit via a logic circuit. A first voltage is compared with a reference voltage to generate a comparison voltage, which is transmitted through the latch and the first delay element. The comparison voltage is monitored at an output of the first delay element. A brown-out condition occurs if the comparison voltage being monitored at the output of the first delay element results from the first voltage being less than the reference voltage.Type: ApplicationFiled: April 28, 2009Publication date: February 9, 2012Inventors: Joel Turchi, Ptacek Karel, Mlcousek Radim
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Publication number: 20120032652Abstract: A method and circuit for generating a clock signal. A power factor correction circuit has n channels operating out of phase and independently. The circuit is able to generate a clock signal for each channel according to the current cycle duration of each channel.Type: ApplicationFiled: April 28, 2009Publication date: February 9, 2012Inventors: Joel Turchi, Stéphanie Conseil
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Patent number: 7977929Abstract: A voltage regulator (10) having an undervoltage protection circuit 11 and a method for protecting against an output voltage out being less than a predetermined level. The voltage regulator has an undershoot limitation circuit (11) coupled between a feedback network (30) and a regulation section (42). A power factor correction circuit (46) is connected to the regulation section. An output voltage out from the power factor correction circuit (46) is fed back to the feedback network (30), which transmits a portion of the output voltage to the undershoot limitation circuit (11). If the output voltage is greater than the predetermined voltage level, a switching circuit portion (34) of the undershoot limitation circuit (11) transmits a normal control signal to the regulation circuit (42). If the output voltage is less than the predetermined voltage level, the switching circuit portion transmits an enhanced control signal to the regulation circuit.Type: GrantFiled: March 2, 2006Date of Patent: July 12, 2011Assignee: Semiconductor Components Industries, LLCInventors: Joel Turchi, Christophe Basso
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Patent number: 7812584Abstract: A regulator circuit and a method for regulating an output voltage. The regulator circuit includes an undervoltage protection stage capable of operating in a plurality of operating modes. In one mode, the undervoltage protection stage compensates for a low undervoltage appearing in the output voltage and in another mode it compensates for a large undervoltage appearing in the output voltage. When the output voltage has a low undervoltage, a portion of the current from a current source is routed to a feedback network to balance the input voltages of the undervoltage protection stage and to place the voltage regulator in a steady state operating mode. When the output voltage has a large undervoltage, the undervoltage protection stage turns on a current sourcing transistor that cooperates with the current from the current source to quickly charge a compensation capacitor and increase the power appearing at the output of the voltage regulator.Type: GrantFiled: April 18, 2006Date of Patent: October 12, 2010Assignee: Semiconductor Components Industries, LLCInventors: Joel Turchi, Christophe Basso
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Patent number: 7782033Abstract: A voltage regulator having an overload protection circuit and a method for protecting against an output voltage being less than a predetermined level. The voltage regulator has an overload protection circuit coupled between a feedback network and a regulation section. A power factor correction circuit is connected to the regulation section. An output voltage from the power factor correction circuit is fed back to the feedback network, which transmits a portion of the output voltage to the overload protection circuit. If the output voltage is less than the predetermined voltage level, a transconductance amplifier generates a current that sets an overload flag. Setting the overload flag initiates a delay timer. If the delay exceeds a predetermined amount of time, the overload protection circuit shuts down the voltage regulator.Type: GrantFiled: March 2, 2006Date of Patent: August 24, 2010Assignee: Semiconductor Components Industries, L.L.C.Inventors: Joel Turchi, Christophe Basso
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Publication number: 20090189573Abstract: A voltage regulator having an overload protection circuit and a method for protecting against an output voltage being less than a predetermined level. The voltage regulator has an overload protection circuit coupled between a feedback network and a regulation section. A power factor correction circuit is connected to the regulation section. An output voltage from the power factor correction circuit is fed back to the feedback network, which transmits a portion of the output voltage to the overload protection circuit. If the output voltage is less than the predetermined voltage level, a transconductance amplifier generates a current that sets an overload flag. Setting the overload flag initiates a delay timer. If the delay exceeds a predetermined amount of time, the overload protection circuit shuts down the voltage regulator.Type: ApplicationFiled: March 2, 2006Publication date: July 30, 2009Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.Inventors: Joel Turchi, Christophe Basso
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Publication number: 20090167365Abstract: A regulator circuit and a method for regulating an output voltage. The regulator circuit includes an undervoltage protection stage capable of operating in a plurality of operating modes. In one mode, the undervoltage protection stage compensates for a low undervoltage appearing in the output voltage and in another mode it compensates for a large undervoltage appearing in the output voltage. When the output voltage has a low undervoltage, a portion of the current from a current source is routed to a feedback network to balance the input voltages of the undervoltage protection stage and to place the voltage regulator in a steady state operating mode. When the output voltage has a large undervoltage, the undervoltage protection stage turns on a current sourcing transistor that cooperates with the current from the current source to quickly charge a compensation capacitor and increase the power appearing at the output of the voltage regulator.Type: ApplicationFiled: April 18, 2006Publication date: July 2, 2009Inventors: Joel Turchi, Christophe Basso
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Publication number: 20090015225Abstract: A voltage regulator (10) having an undervoltage protection circuit 11 and a method for protecting against an output voltage out being less than a predetermined level. The voltage regulator has an undershoot limitation circuit (11) coupled between a feedback network (30) and a regulation section (42). A power factor correction circuit (46) is connected to the regulation section. An output voltage out from the power factor correction circuit (46) is fed back to the feedback network (30), which transmits a portion of the output voltage to the undershoot limitation circuit (11). If the output voltage is greater than the predetermined voltage level, a switching circuit portion (34) of the undershoot limitation circuit (11) transmits a normal control signal to the regulation circuit (42). If the output voltage is less than the predetermined voltage level, the switching circuit portion transmits an enhanced control signal to the regulation circuit.Type: ApplicationFiled: March 2, 2006Publication date: January 15, 2009Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Joel Turchi, Christophe Basso
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Patent number: 7447601Abstract: A power supply controller determines the value of an input power and uses the value of the input power to regulate a value of the output voltage.Type: GrantFiled: February 26, 2004Date of Patent: November 4, 2008Assignee: Semiconductor Components Industries, L.L.C.Inventors: Francois Lhermite, Joel Turchi
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Publication number: 20060290337Abstract: A power supply controller determines the value of an input power and uses the value of the input power to regulate a value of the output voltage.Type: ApplicationFiled: February 26, 2004Publication date: December 28, 2006Inventors: Francois Lhermite, Joel Turchi
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Patent number: 7123494Abstract: A power factor correction (PFC) circuit (10) includes a pulse width modulator (31) operating in response to a clock signal (CLK) for switching a coil current (ICOIL) over a charging period (TCHG) to correct a power factor at a node (32). The coil current discharges over a discharging period (TDSCHG) to develop an output voltage (VOUT) at an output (30). An oscillator (35) generates the clock signal to have a clock period (TCLK) longer than the sum of the charging and discharging periods, thereby operating in a discontinuous mode, and has an input (39) for sensing the input signal to modify the clock period.Type: GrantFiled: May 6, 2003Date of Patent: October 17, 2006Assignee: Semiconductor Components Industries, L.L.C.Inventor: Joel Turchi
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Publication number: 20060087298Abstract: A power factor correction (PFC) circuit (10) includes a pulse width modulator (31) operating in response to a clock signal (CLK) for switching a coil current (ICOIL) over a charging period (TCHG) to correct a power factor at a node (32). The coil current discharges over a discharging period (TDSCHG) to develop an output voltage (VOUT) at an output (30). An oscillator (35) generates the clock signal to have a clock period (TCLK) longer than the sum of the charging and discharging periods, thereby operating in a discontinuous mode, and has an input (39) for sensing the input signal to modify the clock period.Type: ApplicationFiled: May 6, 2003Publication date: April 27, 2006Inventor: Joel Turchi
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Patent number: 6970365Abstract: A power factor correction (PFC) circuit (10) includes a latch (16) having an output that initiates a coil current (ICOIL) in response to a transition edge of a clock signal (CLOCK) to generate a PFC signal (VOUT). An input receives a control signal (TERM). A current modulation circuit (14) has a first input (36) coupled for receiving the PFC signal to establish a charging time (TCH) of the coil current. A second input senses the coil current to establish a duty cycle of the coil current over a period of the clock signal, and an output (38) provides the control signal as a function of the charging time and the duty cycle.Type: GrantFiled: December 12, 2001Date of Patent: November 29, 2005Assignee: JPMorgan Chase Bank, N.A.Inventor: Joel Turchi
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Publication number: 20040239296Abstract: A power factor correction (PFC) circuit (10) includes a latch (16) having an output that initiates a coil current (ICOIL) in response to a transition edge of a clock signal (CLOCK) to generate a PFC signal (VOUT). An input receives a control signal (TERM). A current modulation circuit (14) has a first input (36) coupled for receiving the PFC signal to establish a charging time (TCH) of the coil current. A second input senses the coil current to establish a duty cycle of the coil current over a period of the clock signal, and an output (38) provides the control signal as a function of the charging time and the duty cycle.Type: ApplicationFiled: May 22, 2003Publication date: December 2, 2004Inventor: Joel Turchi
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Publication number: 20020158612Abstract: Voltage regulator (10) provides current sense comparator (18) to detect the normal and standby modes of operation for voltage regulator (10). During a normal mode of operation, current sense comparator (18) de-asserts signal (MODE), causing voltage regulator (10) to regulate the output voltage to a predetermined level. Once the current (Iin) has diminished below a predetermined value, current sense comparator (18) asserts signal (MODE) to indicate a standby mode. During the standby mode, regulator (10) regulates the output voltage (Vout) between first and second reference levels, requiring a quiescent current level much less than the quiescent current level required during normal mode, due to the deactivation of current sense comparator (18) and error amplifier (28) during standby mode. An alternate method of quiescent current reduction uses switched voltage reference (86).Type: ApplicationFiled: April 27, 2001Publication date: October 31, 2002Applicant: Semiconductor Components Industries, LLCInventors: Pierre Andre Genest, Joel Turchi
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Patent number: 6472857Abstract: Voltage regulator (10) provides current sense comparator (18) to detect the normal and standby modes of operation for voltage regulator (10). During a normal mode of operation, current sense comparator (18) de-asserts signal (MODE), causing voltage regulator (10) to regulate the output voltage to a predetermined level. Once the current (Iin) has diminished below a predetermined value, current sense comparator (18) asserts signal (MODE) to indicate a standby mode. During the standby mode, regulator (10) regulates the output voltage (Vout) between first and second reference levels, requiring a quiescent current level much less than the quiescent current level required during normal mode, due to the deactivation of current sense comparator (18) and error amplifier (28) during standby mode. An alternate method of quiescent current reduction uses switched voltage reference (86).Type: GrantFiled: April 27, 2001Date of Patent: October 29, 2002Assignee: Semiconductor Components Industries LLCInventors: Pierre Andre Genest, Joel Turchi
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Patent number: 6392906Abstract: A pwm controller 10 which includes a Vcc node (pin 6); a start-up current source 180 connected to the Vcc node; and a driver circuit 150, 190 also connected to the Vcc node, wherein the pwm controller 10 is arranged to operate in a first phase in which the start-up current source supplies 180 current to the Vcc node but the driver circuit is turned off; a second phase in which the driver circuit 150, 190 is enabled and draws current from the Vcc node; and a third phase in which both the start-up current source 180 and the driver circuit 150, 190 are turned off whereby very little current may be drawn from the Vcc node (pin 6) during the third phase.Type: GrantFiled: May 26, 2000Date of Patent: May 21, 2002Assignee: Semiconductor Components Industries LLCInventors: Francois L'Hermite, Joel Turchi, Josef Halamik
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Patent number: 6385061Abstract: A method and a power conversion apparatus having a substantially direct current input voltage, an output transformer having a primary inductor and at least a secondary winding, and a transistor for controlling the transfer of energy from the primary inductor to the secondary winding and coupled to a controller for switching the transistor on and off at a predetermined rate. A sensor for sensing the power required at the output of the conversion apparatus and for generating a voltage representative thereof is provided, as is provided a sensor for sensing the peak current in the primary inductor and for developing a voltage representative thereof.Type: GrantFiled: February 12, 2001Date of Patent: May 7, 2002Assignee: Semiconductor Components Industries LLCInventors: Joel Turchi, Frantisek Sukup