Abstract: One embodiment relates to an apparatus that includes at least one circuit block and a voltage source configured to supply a first voltage to the at least one circuit block. The apparatus also includes a power delivery unit configured to be selectively activated based on a whether a quantity of power is to be delivered from the power delivery unit to the circuit block. A control unit is configured to, upon a change in power consumption of the at least one circuit block, activate the auxiliary power delivery unit to deliver the quantity of power to the circuit block. The auxiliary power delivery unit can quickly supply large currents since it does not necessarily rely on slow control loops using voltage sensing. Rather, the auxiliary power delivery unit often delivers pre-calculated current profiles to respond to the timing characteristic of the change of power consumption and of the voltage regulator.

Abstract: One or more embodiments relate to an apparatus comprising: a first transistor including a channel in a fin; and a second transistor including a channel in a fin, the channel of the first transistor being doped with a first dopant of a first polarity and counter-doped with a second dopant of a second polarity opposite to the first polarity, a concentration of the first dopant being approximately equal to a concentration of the second dopant, wherein the first transistor and the second transistor are of a same conductivity type.

Abstract: One or more embodiments relate to a method comprising: raising a potential of a first bit line and a second bit line; switching on a first n-channel access transistor coupled between the first bit line and a first node of a first inverter; switching on a second n-channel access transistor coupled between the second bit line and a second node of a second inverter; and reading a static random access memory (SRAM) cell including the first inverter and the second inverter by sensing a potential on the first bit line and a potential on the second bit line.

Abstract: One or more embodiments relate to an apparatus comprising: a first transistor including a channel in a fin; and a second transistor including a channel in a fin, the channel of the first transistor being doped with a first dopant of a first polarity and counter-doped with a second dopant of a second polarity opposite to the first polarity, a concentration of the first dopant being approximately equal to a concentration of the second dopant, wherein the first transistor and the second transistor are of a same conductivity type.

Abstract: One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor.

Abstract: One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.

Abstract: One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor.

Abstract: One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.

Abstract: One or more embodiments relate to a static random access memory cell comprising: a first inverter including a first n-channel pull-down transistor coupled between a first node and a ground voltage; a second inverter including a second n-channel pull-down transistor coupled between a second node and the ground voltage; a first n-channel access transistor coupled between a first bit line and the first node of the first inverter, a fin of the first n-channel access transistor having a lower charge carrier mobility than a fin of the first n-channel pull-down transistor; and a second n-channel access transistor coupled between a second bit line and the second node of the second inverter, a fin of the second n-channel access transistor having a lower charge carrier mobility than a fin of the second n-channel pull-down transistor.

Abstract: One embodiment relates to an apparatus that includes at least one circuit block and a voltage source configured to supply a first voltage to the at least one circuit block. The apparatus also includes a power delivery unit configured to be selectively activated based on a whether a quantity of power is to be delivered from the power delivery unit to the circuit block. A control unit is configured to, upon a change in power consumption of the at least one circuit block, activate the auxiliary power delivery unit to deliver the quantity of power to the circuit block. The auxiliary power delivery unit can quickly supply large currents since it does not necessarily rely on slow control loops using voltage sensing. Rather, the auxiliary power delivery unit often delivers pre-calculated current profiles to respond to the timing characteristic of the change of power consumption and of the voltage regulator.

Abstract: A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor.

Abstract: A circuit arrangement may include a scan test input stage having a test input for receiving a test signal, wherein the scan test input stage can be switched in high-impedance state; a data input stage having a data input for receiving a data signal, wherein the data input stage can be switched in high-impedance state. The circuit arrangement may further include a latch coupled to at least one output of the scan test input stage and to at least one output of the data input stage; and a drive circuit, which is configured to generate a pulsed clock signal for the data input stage and a signal for driving the scan test input stage.

Abstract: A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs.

Abstract: A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor.

Abstract: A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison.

Abstract: An integrated circuit includes functional blocks, a power control unit controlling the provision of power to the different functional blocks of the integrated circuit, a detecting unit detecting if a turned off functional block is to be turned on, and a clock signal control unit controlling the provision of the clock signal for the functional blocks. The clock signal control unit interrupts the clock signal for the activated functional blocks of the integrated circuit for a predetermined number of clock cycles. The power control unit provides power to the turned off functional block during the interrupted clock cycles.

Abstract: A digital circuit unit includes at least one circuit block, a voltage source for supplying the circuit block, a detection unit, which monitors the change of current drain by the at least one circuit block, an additional power consumption unit, which upon activation consumes power in addition to the at least one circuit block, and a control unit, which controls the power consumption unit in such a way that upon a change in the power consumption of the circuit block the power consumption unit is activated and drains current.

Abstract: A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison.

Abstract: An integrated circuit, comprising a first data retention element configured to retain the data, the first data retention element having a first setup time, and a second data retention element configured to retain the data, the second data retention element having a second setup time, the second data retention element further having a data input. The second data retention element is connected in parallel with the first data retention element, and the second data retention element is configurable via the data input such that the second setup time is longer than the first setup time.

Abstract: A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs.