Patents by Inventor Joerg Berthold

Joerg Berthold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070002619
    Abstract: The non-volatile memory cell has a volatile memory means for storing an item of binary information. Furthermore, the memory cell comprises only a single programmable resistance element for non-volatile saving of the stored information and a means for saving the information in the resistance element. A means for retrieving the saved information is additionally present.
    Type: Application
    Filed: June 28, 2006
    Publication date: January 4, 2007
    Inventors: TIM SCHOENAUER, Michael Kund, Thomas Niedermeier, Joerg Berthold
  • Publication number: 20070002618
    Abstract: A memory element comprises a resistance element having a first resistance value in a first state and a second resistance value in a second state, it being possible to convert the resistance element from the first state into the second state and from the second state into the first state and the first resistance value and the second resistance value being different, a current generating device, coupled to a first terminal of the resistance element, the current generating device being designed to generate a current with a first amplitude through the resistance element when a predetermined potential is present at a second terminal of the resistance element, in order to convert the resistance element into the first state for setting the first resistance value, or to generate a current with a second amplitude through the resistance element when the predetermined potential is present at the second terminal of the resistance element, in order to convert the resistance element into the second state for setting the se
    Type: Application
    Filed: June 28, 2006
    Publication date: January 4, 2007
    Inventors: TIM SCHOENAUER, Michael Kund, Thomas Niedermeier, Joerg Berthold
  • Patent number: 7110932
    Abstract: A method and circuit arrangement for determining performance of a digital circuit to a critical degree by the transit time of signals of the longest signal path, also called the critical path. Since the signal transit time is influenced by the operating voltage, by regulating the operating voltage, to compensate for the effects caused by temperature and process fluctuations on the signal transit time in the digital circuit. In particular, the operating voltage can be regulated as a function of the signal transit time in such a way that a required minimum operating frequency can always be achieved. To determine signal transit time, the digital circuit has associated with it a number of replicas of the critical path in the digital circuit upon which the signal transit time is determined. In order to determine the transit time, the signal path replicas are exposed to the same operating conditions as the digital circuit.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: September 19, 2006
    Assignee: Infineon Technologies AG.
    Inventors: Joerg Berthold, Henning Lorch
  • Publication number: 20060119406
    Abstract: The flip-flop according to the invention serves for storing an item of logic state information and has at least one data input and at least one data output. The flip-flop comprises at least one latch stage for storing the state information if the flip-flop is switched on. Furthermore, the flip-flop according to the invention comprises at least one memory cell having a capacitance as storage element. In this case, the at least one memory cell serves for storing the state information if the flip-flop is switched off.
    Type: Application
    Filed: November 15, 2005
    Publication date: June 8, 2006
    Inventors: Stephan Henzler, Joerg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel, Christian Pacha
  • Patent number: 6570439
    Abstract: In order to achieve reliable operation despite the greater interference susceptibility of a circuit (1) at a reduced power supply, in addition to a global power supply path (6, 7) to supply the circuit (1) in operating state, a rest state power supply path (10, 11) is provided with which the circuit (1) is connected in particular via transistor diodes (14, 15). As soon as the circuit (1) by way of first switches (12, 13) is separated from the global power supply path (6, 7), because of the voltage loss in the transistor diodes (14, 15) it is supplied by the rest state power supply path (10, 11) which is provided exclusively to supply circuit parts (1) set into rest state and on which therefore fewer current or voltage peaks can occur.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: May 27, 2003
    Assignee: Infineon Technologies AG
    Inventor: Joerg Berthold
  • Publication number: 20030037307
    Abstract: A method and circuit arrangement for determining performance of a digital circuit to a critical degree by the transit time of signals of the longest signal path, also called the critical path. Since the signal transit time is influenced by the operating voltage, by regulating the operating voltage, to compensate for the effects caused by temperature and process fluctuations on the signal transit time in the digital circuit. In particular, the operating voltage can be regulated as a function of the signal transit time in such a way that a required minimum operating frequency can always be achieved. To determine signal transit time, the digital circuit has associated with it a number of replicas of the critical path in the digital circuit upon which the signal transit time is determined. In order to determine the transit time, the signal path replicas are exposed to the same operating conditions as the digital circuit.
    Type: Application
    Filed: June 13, 2002
    Publication date: February 20, 2003
    Inventors: Joerg Berthold, Henning Lorch
  • Publication number: 20020158683
    Abstract: In order to achieve reliable operation despite the greater interference susceptibility of a circuit (1) at a reduced power supply, in addition to a global power supply path (6, 7) to supply the circuit (1) in operating state, a rest state power supply path (10, 11) is provided with which the circuit (1) is connected in particular via transistor diodes (14, 15). As soon as the circuit (1) by way of first switches (12, 13) is separated from the global power supply path (6, 7), because of the voltage loss in the transistor diodes (14, 15) it is supplied by the rest state power supply path (10, 11) which is provided exclusively to supply circuit parts (1) set into rest state and on which therefore fewer current or voltage peaks can occur.
    Type: Application
    Filed: April 25, 2002
    Publication date: October 31, 2002
    Applicant: Infineon Technologies AG
    Inventor: Joerg Berthold
  • Patent number: 5371423
    Abstract: A tri-state capable driver circuit or totem pole circuit is formed in BiCMOS technology and includes a selection circuit, first and second drive circuits, and first and second bipolar transistors. A short circuit unit is connected between the base and the emitter of the first bipolar transistor to prevent excessively high inhibit voltages across the base-emitter junction of the first bipolar transistor. The operation of the short circuit unit depends upon signals received at the tri-state activation input.
    Type: Grant
    Filed: August 17, 1993
    Date of Patent: December 6, 1994
    Assignee: Siemens Aktiengesellschaft
    Inventors: Joerg Berthold, Gerhard Nebel, Doris Schmitt-Landsiedel