Abstract: A center console for a vehicle, having at least one rearwardly situated armrest and having at least one functional unit. In order to enable an existing structural space to be utilized optimally, and at the same time optimize the center console with regard to its storage space, the functional unit is mounted to be linearly movable between a rearward rest position, in which the functional unit is arranged at least predominantly under the armrest, and at least one forward functional position, in which the functional unit is at least predominantly forwardly offset in relation to the armrest.

Abstract: A center console for a vehicle, having a storage trough which extends over at least a predominant part of a length of the center console and which has a longitudinally extending side wall that laterally delimits a storage space of the storage trough. In order to optimize an ability of the center console to store articles, the center console has a holding unit which is arranged in the storage space of the storage trough and on the side wall and by use of which at least one article can be temporarily clamped between the holding unit and the side wall.

Abstract: A center console for a vehicle, having at least one storage trough which extends over at least a predominant part of a length of the center console. In order to provide a center console that is of simplified construction and is optimized in terms of its characteristics, the center console has at least one functional unit which is connected to an elevated rearward end portion of the storage trough and which, proceeding from the rearward end portion, extends forwardly in an overhanging manner at least over a part of a length of the storage trough.

Abstract: A center console for a vehicle, having a storage trough which extends over at least a predominant part of a length of the center console. In order to provide a center console that can be easily configured by a user as required, the center console has at least two different electrical functional units which each individually are selectively arrangeable at least partially in a storage space of the storage trough.

Abstract: A center console for a vehicle has a storage trough, which extends over at least a predominant part of a length of the center console, and a storage container, which is insertable into the storage trough and which has an upper entrance opening. In order to provide a center console and front seat assembly for a vehicle that are individually configurable in terms of their characteristics, the storage container has a roller shutter for closing the entrance opening.

Abstract: A sort device includes a compare unit on one level of a hierarchical structure that includes a plurality of levels. The compare unit to compare one beat of one record with another beat of another record to provide a winner beat. The sort device further includes another compare unit on another level of the hierarchical structure to provide a further beat to the compare unit, and a request pipe to be used to request that the other compare unit provide the further beat to the compare unit.

Abstract: Multi-cycle key compare units. A compare unit includes a comparator, additional compare logic and at least one pair of buffers which provide input to the comparator. The compare unit sorts variable length records in streaming mode without the need for complex state machines to maintain state relating to the comparing. A record may have a variable length key and optional variable length data. The record and/or the key is split into fixed, pre-defined lengths. The total key and record lengths are unknown to the comparator of the compare unit.

Abstract: A logic device includes a compare unit at one level of a plurality of levels of a hierarchical structure to be used in sorting of records. The compare unit includes a buffer pair in which one or more buffers of the buffer pair are adapted to store at least one record. The logic device further includes another compare unit on another level of the plurality of levels of the hierarchical structure. The other compare unit includes another buffer pair in which one or more other buffers of the other buffer pair are adapted to store a portion of a record. A size of the one or more other buffers of the other buffer pair is insufficient to store the entire record. The one compare unit and the other compare unit are adapted to sort a plurality of records.

Abstract: A compare unit includes an array including a plurality of buffer pairs to receive records on one level of a plurality of levels of a hierarchical structure. A comparator is coupled to the array, and the comparator includes one input to receive one beat of one record from one buffer of a selected buffer pair of the plurality of buffer pairs coupled to the comparator. The comparator further includes another input to receive another beat of another record from another buffer of the selected buffer pair, and logic coupled to the one input and the other input to compare the one beat and the other beat to obtain a winner beat of the compare.

Abstract: A method, computer program product, and computer system for providing a comparison result vector of a predefined number of elements w resulting from comparison of multiple vectors of compressed data within a processor comprising registers of same size m is provided. Vector elements of the comparison result vector are stored in a register of the registers. Zero bits are padded between vector elements of each of the comparison result vectors. A compare bit result vector indicative of the vector elements is generated for accessing the results of the comparison in the comparison result vector.

Abstract: The present disclosure relates performing of comparisons between a first and a second vector. The memory location has a size or length of m bits. A compare block to compare two single bits is used. The compare block comprises: two input bits associated to one of the bits from the first and the second vector respectively; a greater than input bit and a lower than input bit; a cascade enable input bit to control if the greater than input bit and the lower than input bit are considered; a greater than result bit, a lower than result bit, and an equal result bit. A daisy chaining of m of the one-bit compare blocks is performed such that the result bits of one compare block represents the compare result of the previous compare blocks in the chain.

Abstract: A computer program product for data compression is provided. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and executable by a processing circuit to cause the processing circuit to execute software compression for first requests for data compression that have respective sizes below a predefined threshold, forward second requests for data compression having respective sizes above the predefined threshold to a hardware accelerator and maintain a persistence of a compression dictionary used for executing the second requests across executions of the first and second requests.

Abstract: The present disclosure relates performing of comparisons between a first and a second vector. The memory location has a size or length of m bits. A compare block to compare two single bits is used. The compare block comprises: two input bits associated to one of the bits from the first and the second vector respectively; a greater than input bit and a lower than input bit; a cascade enable input bit to control if the greater than input bit and the lower than input bit are considered; a greater than result bit, a lower than result bit, and an equal result bit. A daisy chaining of m of the one-bit compare blocks is performed such that the result bits of one compare block represents the compare result of the previous compare blocks in the chain.

Abstract: The present disclosure relates a method, computer program product, and computer system to provide a comparison result vector of a predefined number of elements w resulting from comparison of multiple vectors of compressed data within a processor comprising registers of same size m. Vector elements of the comparison result vector are stored in a register of the registers. Zero bits are padded between vector elements of each of the comparison result vectors. A compare bit result vector indicative of the vector elements is generated for accessing the results of the comparison in the comparison result vector.

Abstract: Multi-cycle key compare units. A compare unit includes a comparator, additional compare logic and at least one pair of buffers which provide input to the comparator. The compare unit sorts variable length records in streaming mode without the need for complex state machines to maintain state relating to the comparing. A record may have a variable length key and optional variable length data. The record and/or the key is split into fixed, pre-defined lengths. The total key and record lengths are unknown to the comparator of the compare unit.

Abstract: A compare unit includes an array including a plurality of buffer pairs to receive records on one level of a plurality of levels of a hierarchical structure. A comparator is coupled to the array, and the comparator includes one input to receive one beat of one record from one buffer of a selected buffer pair of the plurality of buffer pairs coupled to the comparator. The comparator further includes another input to receive another beat of another record from another buffer of the selected buffer pair, and logic coupled to the one input and the other input to compare the one beat and the other beat to obtain a winner beat of the compare.

Abstract: A logic device includes a compare unit at one level of a plurality of levels of a hierarchical structure to be used in sorting of records. The compare unit includes a buffer pair in which one or more buffers of the buffer pair are adapted to store at least one record. The logic device further includes another compare unit on another level of the plurality of levels of the hierarchical structure. The other compare unit includes another buffer pair in which one or more other buffers of the other buffer pair are adapted to store a portion of a record. A size of the one or more other buffers of the other buffer pair is insufficient to store the entire record. The one compare unit and the other compare unit are adapted to sort a plurality of records.

Abstract: A sort device includes a compare unit on one level of a hierarchical structure that includes a plurality of levels. The compare unit to compare one beat of one record with another beat of another record to provide a winner beat. The sort device further includes another compare unit on another level of the hierarchical structure to provide a further beat to the compare unit, and a request pipe to be used to request that the other compare unit provide the further beat to the compare unit.

Abstract: A computing system includes a host processor, an access processor having a command port, a near memory accelerator, and a memory unit. The system is adapted to run a software program on the host processor and to offload an acceleration task of the software program to the near memory accelerator. The system is further adapted to provide, via the command port, a first communication path for direct communication between the software program and the near memory accelerator, and to provide, via the command port and the access processor, a second communication path for indirect communication between the software program and the near memory accelerator. A related computer implemented method and a related computer program product are also disclosed.

Abstract: A computing system includes a host processor, an access processor having a command port, a near memory accelerator, and a memory unit. The system is adapted to run a software program on the host processor and to offload an acceleration task of the software program to the near memory accelerator. The system is further adapted to provide, via the command port, a first communication path for direct communication between the software program and the near memory accelerator, and to provide, via the command port and the access processor, a second communication path for indirect communication between the software program and the near memory accelerator. A related computer implemented method and a related computer program product are also disclosed.