Abstract: An approach is provided in which a hardware accelerator receives a request to decompress a data stream that includes multiple deflate blocks and multiple deflate elements compressed according to block-specific compression configuration information. The hardware accelerator identifies a commit point that is based upon an interruption of a first decompression session of the data stream and corresponds to one of the deflate blocks. As such, the hardware accelerator configures a decompression engine based upon the corresponding deflate block's configuration information and, in turn, recommences decompression of the data stream at an input bit location corresponding to the commit point.

Abstract: Embodiments relate to providing a data stream interface for offloading the inflation/deflation processing of data to a stateless compression accelerator. An aspect includes transmitting a request to inflate or deflate a data stream to a compression accelerator. The request may include references to an input buffer for storing input data from the data stream, an output buffer for storing processed input data, and a state data control block for storing a stream state. The stream state is provided to the compression accelerator to continue processing the data stream responsive to the request being a subsequent request. The compression accelerator is instructed to store a current stream state in the state data control block responsive to the request being a non-final request. Accordingly, the current stream state is received from the compression accelerator responsive to the request being a non-final request. The processed input data is received from the compression accelerator.

Abstract: Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.

Abstract: Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.

Abstract: A preprocessing unit includes a data receiver to receive a data packet containing packet information, application data, and application data information, a relevance checker to determine relevance of the data packet in dependence on the packet information, an output module to output preprocessor output data, and a first controller to control output of preprocessor output data in dependence on the relevance of the data packet. In order to discard redundant data, thereby reducing the load of the memory, bus, and CPU of the computer system, the preprocessing unit further comprises a redundancy checker to determine redundancy of the application data preferably and a second controller to control output of preprocessor output data in dependence on the redundancy of the application data.

Abstract: Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.

Abstract: Embodiments relate to providing a data stream interface for offloading the inflation/deflation processing of data to a stateless compression accelerator. An aspect includes transmitting a request to inflate or deflate a data stream to a compression accelerator. The request may include references to an input buffer for storing input data from the data stream, an output buffer for storing processed input data, and a state data control block for storing a stream state. The stream state is provided to the compression accelerator to continue processing the data stream responsive to the request being a subsequent request. The compression accelerator is instructed to store a current stream state in the state data control block responsive to the request being a non-final request. Accordingly, the current stream state is received from the compression accelerator responsive to the request being a non-final request. The processed input data is received from the compression accelerator.

Abstract: A unit for storing items in a motor vehicle interior includes a main storage compartment and a docking station for a portable electronic device such as a smart phone or a navigation device. A main cover is movably attached to the storage compartment to enclose the main storage compartment, and a docking cover encloses a sub-portion of the storage compartment. The docking cover is movable to an in-service position wherein its underside is exposed. A device holder is attached to the underside of the docking cover for holding a mobile electronic device in an access position when in the docking cover is in the in-service position. The docking cover and the portion are inset relative to a perimeter of the storage compartment, so that the docking station forms a portion of a main perimeter of the storage compartment.

Abstract: A preprocessing unit includes a data receiver to receive a data packet containing packet information, application data, and application data information, a relevance checker to determine relevance of the data packet in dependence on the packet information, an output module to output preprocessor output data, and a first controller to control output of preprocessor output data in dependence on the relevance of the data packet. In order to discard redundant data, thereby reducing the load of the memory, bus, and CPU of the computer system, the preprocessing unit further comprises a redundancy checker to determine redundancy of the application data preferably and a second controller to control output of preprocessor output data in dependence on the redundancy of the application data.

Abstract: A foldable holder for a beverage container comprises a fastening plate, a supporting ring coupled pivotably to the fastening plate, a holding bracket coupled pivotably to the fastening plate, and a supporting plate coupled pivotably to the holding bracket. The supporting ring and the holding bracket share a pivot axis extending from the fastening plate. The supporting plate is coupled to a remote end of the holding bracket so as to be pivotable counter to a pivoting direction of the supporting ring. The holding bracket and the supporting plate are disposed radially within the supporting ring when folded into a retracted state.

Abstract: Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.

Abstract: Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.

Abstract: A foldable holder for a beverage container comprises a fastening plate, a supporting ring coupled pivotably to the fastening plate, a holding bracket coupled pivotably to the fastening plate, and a supporting plate coupled pivotably to the holding bracket. The supporting ring and the holding bracket share a pivot axis extending from the fastening plate. The supporting plate is coupled to a remote end of the holding bracket so as to be pivotable counter to a pivoting direction of the supporting ring. The holding bracket and the supporting plate are disposed radially within the supporting ring when folded into a retracted state.

Abstract: A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.

Abstract: The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.

Abstract: A multi-function light switch unit mountable to an interior panel of an automotive vehicle has a rotatable outer ring controlling a main headlamp, two pushbutton panels within the outer ring controlling additional lights, and an extendable module within the outer ring having at two rotary controllers for controlling other lights. The extendable module is movable with between an extended position wherein it projects from the front surface of the light switch unit such that the rotary controllers are exposed in a manually operative position in front of the push button panels, and a retracted position wherein the rotary controllers are behind the front surface of the light switch unit.

Abstract: A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.

Abstract: A multi-function light switch unit mountable to an interior panel of an automotive vehicle has a rotatable outer ring controlling a main headlamp, two pushbutton panels within the outer ring controlling additional lights, and an extendable module within the outer ring having at two rotary controllers for controlling other lights. The extendable module is movable with between an extended position wherein it projects from the front surface of the light switch unit such that the rotary controllers are exposed in a manually operative position in front of the push button panels, and a retracted position wherein the rotary controllers are behind the front surface of the light switch unit.

Abstract: The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.

Abstract: The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.