Abstract: A differential amplifier circuit has two input transistors, a load element, and a current source. A terminal for an input voltage is connected to a control terminal of a first input transistor. A terminal for a reference voltage is connected to a control terminal of a second input transistor. The two input transistors are connected in parallel between the load element and a terminal of the current source. A terminal for an internal reference potential is connected to a further terminal of the current source. A regulating circuit, is connected to the terminal for the voltage and to the terminal for the reference potential, and regulates the potential of the circuit dependent on changes in the reference voltage. Fluctuations of the reference voltage are compensated by regulation of the internal reference potential. As a result, the operating point of the circuit is stabilized independently of fluctuations of the reference voltage.

Abstract: An integrated semiconductor circuit includes a transistor and a strip conductor (11). The transistor includes a first (1) and a second source/drain region (2) and a gate electrode. The strip conductor (11) is electrically insulated from a semiconductor body at least by a gate dielectric and forms the gate electrode in the area of the transistor. The strip conductor (11) extends along a first direction (x) in the area of the transistor. The second source/drain region (2) is arranged offset with respect to the first source/drain region (1) in the first direction (x). The transistor thus formed has an inversion channel (K1) that only extends between two corner areas (1a, 2a) facing one another of the first and of the second source/drain region, i.e. is much narrower than in the case of a conventional transistor.

Abstract: An integrated semiconductor circuit includes a cell array having memory cells which can be read by word lines and bit lines. Two bit lines in each case are connected to inputs of the same signal amplifier. In order to compensate for parasitic capacitances which arise at thin sidewall insulations between the patterned word lines and adjacent bit line contacts which connect the bit lines located at a higher level to the active regions located at a deeper level, two additional word lines and dummy contacts of the bit lines are dummy contacts lead past this additional word lines. The additional parasitic capacitances produced by the dummy contacts alter the electrical potential of the respective reference bit line at the signal amplifier in the same way as the parasitic capacitances of activated bit lines, as a result of which the measured differential potential is corrected with respect to the parasitic effects.

Abstract: An integrated semiconductor memory includes memory cells that store a first data record has at least one datum with a first or second data value and a second data record has at least one datum with the first or second data value. The integrated semiconductor memory has a combination circuit that generates the third data record on the output side from the data records fed to the combination circuit on the input side to ascertain based on the third data record whether the first and second data records have been fed to the combination circuit on the input side. The combination circuit generates the datum of the third data record with the first data value, if the first and second data records were fed to the combination circuit on the input side.

Abstract: A memory includes: a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address fuse units, each having a plurality of fusible links and being operable to store a replacement address, each replacement address identifying one of the storage elements of the memory array to be replaced by an associated one of the replacement storage elements and forming a respective 2m bit row or 2n bit column of a fuse array; a vector generator operable to produce a 2n bit row vector based on the rows of the fuse array and to produce a 2m bit column vector based on the columns of the fuse array; and a compression unit operable to produce a row checksum from the row vector and to produce a column checksum from the column vector.

Abstract: An integrated semiconductor circuit can have memory cells, which can be read by word lines and bit lines. Two mutually adjacent bit lines in each case are connected to inputs of the same signal amplifier. In order to compensate for parasitic capacitors, which arise at thin sidewall insulations between the patterned word lines and adjacent bit line contacts, additional contact structures which lead past the word lines and represent dummy contacts can be provided. The additional parasitic capacitances produced by the dummy contact alter the electrical potential of the respective reference bit line at the signal amplifier like the parasitic capacitances of activated bit lines, as a result of which the measured differential potential can be corrected with respect to the parasitic effects.

Abstract: In a driver circuit having a plurality of drivers for driving signals in parallel, the drivers are each connected to an input signal line for receiving a respective input signal and to an output signal line for outputting a respective driven output signal. An output signal line of one of the drivers may be connected, via a switch or switching means, to an output signal line of another of the drivers. A control circuit is connected to one of the drivers and is used to drive the switch or switching means in such a manner that the switching means can be activated, for charge equalization, by the control circuit following a driving operation in one of the drivers. A respective associated memory circuit, by which an associated logic circuit for driving one of the switch or switching means is connected to the relevant output signal line, is connected to the respective output signal line. Overall power consumption of the driver circuit can be minimized.

Abstract: Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.

Abstract: An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input signal. The current pulse circuit is connected to an output terminal via an interconnect for carrying a current. In the test operating state, the current pulse circuit generates at least one first current pulse with a first, predetermined time duration in a first test cycle and at least one second current pulse with a second, unknown time duration in a subsequent second test cycle. In addition to a first current flowing on the interconnect in the normal operating state, a second current flows on the interconnect during the first test cycle and a third current flows during the second test cycle in the test operating state.

Abstract: An integrated circuit includes a circuit component, a first control circuit and a switchable resistance network. An input voltage is fed to the circuit component on the input side. A control signal generated by the first control circuit is fed to the control terminal of the circuit component. With the switchable resistance network, the first resistance or the second resistance is connected between an output terminal of the circuit component and the output terminal of the integrated circuit to generate a voltage drop between the input side and the output terminal of the circuit component. The integrated circuit makes it possible to generate a current at the output terminal of the circuit component in a manner dependent on the control signal and the voltage dropped between the input side and the output terminal of the circuit component. Families of characteristic curves of transistors of an integrated circuit are determined by the integrated circuit.

Abstract: An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage generator circuit. The current generator circuit is connected to an output terminal via an interconnect. A first current flows on the interconnect in a test operating state of the integrated circuit. The current generator circuit generates a first partial current in a first test cycle of a test operating state and a second partial current in a subsequent second test cycle. The partial currents are each superposed on the first current on the interconnect. Consequently, three currents occur at the output terminal during the test operating state. The internally generated input voltage of the current generator circuit is determined from the three currents and the reference voltage.

Abstract: A voltage generator arrangement supplies a largely constant output voltage with a high current driver capability. A bandgap reference circuit drives a voltage generator on the output side, if necessary via an impedance converter. The bandgap reference circuit and the impedance converter on the one hand, and the voltage generator on the other hand, are connected to different reference ground potential lines. The voltage generator on the output side is preceded by a correction circuit, which corrects for the voltage drop on that reference ground potential line to which the output-side voltage generator is connected. The voltage generator arrangement is suitable for a greater integration density.

Abstract: A voltage generator arrangement supplies a largely constant output voltage with a high current driver capability. A bandgap reference circuit is downstream from an impedance converter and downstream a voltage generator. The bandgap reference circuit and the impedance converter on the one hand and the voltage generator on the other hand are connected to different reference ground potential line. The impedance converter contains a charge pump circuit to provide increased control potential, which drives the voltage generator. The voltage generator in contrast produces a reduced output potential. The influence of any voltage drop on that reference ground potential line to which the voltage generator is connected in the output potential is thus likewise reduced.

Abstract: A test system and a method for testing an integrated circuit determines the synchronization of the integrated circuit by a current measurement rather than conventionally in the time domain. The present principle is based on the insight that the current consumption of a DUT given simultaneous driving of data on a common data channel from the DUT and from the tester is dependent on a superposition of both signals. Accordingly, highly accurate conclusions about the phase angle of the two signals with respect to one another can be drawn from the present current consumption. The principle presented can be applied particularly to DDR-SDRAMs with a low outlay.

Abstract: A differential amplifier circuit has two input transistors, a load element, and a current source. A terminal for an input voltage is connected to a control terminal of a first input transistor. A terminal for a reference voltage is connected to a control terminal of a second input transistor. The two input transistors are connected in parallel between the load element and a terminal of the current source. A terminal for an internal reference potential is connected to a further terminal of the current source. A regulating circuit, is connected to the terminal for the voltage and to the terminal for the reference potential, and regulates the potential of the circuit dependent on changes in the reference voltage. Fluctuations of the reference voltage are compensated by regulation of the internal reference potential. As a result, the operating point of the circuit is stabilized independently of fluctuations of the reference voltage.

Abstract: A circuit configuration has a first driver stage for feeding in an input signal and for outputting an amplified signal. A second driver stage, which is connected in parallel with the first driver stage, is fed, on the input side, both the input signal and a control signal from a reference circuit connected upstream. The reference circuit compares the feedback level of an output signal, which level is present at one of its inputs, with the level of the input signal present at its other input and generates the control signal for driving the driver stage in the event that the level of the output signal is lower than the level of the input signal. As a result, the driver stage is connected for additional amplification of the input signal.

Abstract: In a driver circuit having a plurality of drivers for driving signals in parallel, the drivers are each connected to an input signal line for receiving a respective input signal and to an output signal line for outputting a respective driven output signal. An output signal line of one of the drivers may be connected, via a switch or switching means, to an output signal line of another of the drivers. A control circuit is connected to one of the drivers and is used to drive the switch or switching means in such a manner that the switching means can be activated, for charge equalization, by the control circuit following a driving operation in one of the drivers. A respective associated memory circuit, by which an associated logic circuit for driving one of the switch or switching means is connected to the relevant output signal line, is connected to the respective output signal line. Overall power consumption of the driver circuit can be minimized.

Abstract: An integrated memory contains a memory cell array, which has word lines and bit lines, and a read/write amplifier, which is connected to the bit lines for the assessing and amplifying data signals. A voltage generator circuit generates a voltage supply for application to the read/write amplifier. A potential difference is applied to the read/write amplifier using different supply potentials. The voltage generator circuit increases the potential difference applied to the read/write amplifier for a limited period of time during an assessment and amplification operation of the read/write amplifier. Charge-dependent control is implemented in the voltage generator circuit. An assessment and amplification operation can be carried out at a comparatively high switching speed and a low power consumption is possible.

Abstract: A circuit configuration for the bit-parallel outputting the bits of a data word includes at least two signal lines for feeding the data signals representing the bits of the data word to driver stages and to a reference circuit. Further driver stages are connected in parallel with the driver stages and have inputs connected to the control device. The control device establishes the signal states of the data signals to be transferred on each signal line and generates a control signal depending on the type and number of the signal state changes of bit sequences to be transferred. It is possible to drive the driver stages that assigned to the signal line for which a signal state change is present.

Abstract: An integrated semiconductor circuit can have memory cells, which can be read by word lines and bit lines. Two mutually adjacent bit lines in each case are connected to inputs of the same signal amplifier. In order to compensate for parasitic capacitors, which arise at thin sidewall insulations between the patterned word lines and adjacent bit line contacts, additional contact structures which lead past the word lines and represent dummy contacts can be provided. The additional parasitic capacitances produced by the dummy contact alter the electrical potential of the respective reference bit line at the signal amplifier like the parasitic capacitances of activated bit lines, as a result of which the measured differential potential can be corrected with respect to the parasitic effects.