Abstract: An electrically conductive, oxidic target material includes a proportion of substoichiometric molybdenum oxide phases of at least 60% by volume, an MoO2 phase in a proportion of 2-20% by volume, and optionally an MoO3 phase in a proportion of 0-20% by volume. The substoichiometric molybdenum oxide phase proportion is formed by one or more substoichiometric MoO3-y phase(s), where y is in each case in a range from 0.05 to 0.25. A process for producing the target material and a process for using the target material are also provided.

Abstract: A sputtering target containing molybdenum and at least one metal from the group tantalum and niobium. The average content of tantalum and/or niobium is from 5 to 15 at % and the molybdenum content is greater than or equal to 80 at %. The sputtering target has at least a matrix with an average molybdenum content of greater than or equal to 92 at % and particles which are composed of a solid solution containing at least one metal from the group of tantalum and niobium, and molybdenum, with an average molybdenum content of greater than or equal to 15 at % and are embedded in the matrix. There is also described a method of producing a sputtering target.

Abstract: A metallization for a thin-film component includes at least one layer composed of an Mo-based alloy containing Al and Ti and usual impurities. A process for producing a metallization includes providing at least one sputtering target, depositing at least one layer of an Mo-based alloy containing Al and Ti and usual impurities, and structuring the metallization by using at least one photolithographic process and at least one subsequent etching step. A sputtering target is composed of an Mo-based alloy containing Al and Ti and usual impurities. A process for producing a sputtering target composed of an Mo-based alloy includes providing a powder mixture containing Mo and also Al and Ti and cold gas spraying (CGS) of the powder mixture onto a suitable support material.

Abstract: A sputtering target containing molybdenum and at least one metal from the group tantalum and niobium. The average content of tantalum and/or niobium is from 5 to 15 at % and the molybdenum content is greater than or equal to 80 at %. The sputtering target has at least a matrix with an average molybdenum content of greater than or equal to 92 at % and particles which are composed of a solid solution containing at least one metal from the group of tantalum and niobium, and molybdenum, with an average molybdenum content of greater than or equal to 15 at % and are embedded in the matrix. There is also described a method of producing a sputtering target.

Abstract: A bicycle servicing system includes: a transceiver device for arrangement on a bicycle; a bicycle data processing device arranged on the bicycle and connected with the transceiver device; a stationary data processing device for processing bicycle- and/or cyclist-specific data received from the transceiver device, the data processing device being adapted to be in communication with the transceiver device via mobile data transmission; and a data output device for outputting data transmitted from the data processing device, the data output device being adapted to be in communication with the data processing device via mobile data transmission, and/or a further data processing device for further processing of the data transmitted from the data processing device, the further data processing device being adapted to be in communication with the data processing device via data transmission.

Abstract: A metallization for a thin-film component includes at least one layer composed of an Mo-based alloy containing Al and Ti and usual impurities. A process for producing a metallization includes providing at least one sputtering target, depositing at least one layer of an Mo-based alloy containing Al and Ti and usual impurities, and structuring the metallization by using at least one photolithographic process and at least one subsequent etching step. A sputtering target is composed of an Mo-based alloy containing Al and Ti and usual impurities. A process for producing a sputtering target composed of an Mo-based alloy includes providing a powder mixture containing Mo and also Al and Ti and cold gas spraying (CGS) of the powder mixture onto a suitable support material.

Abstract: A sputtering target is composed of an Mo alloy containing at least one metal of group 5 of the Periodic Table, where the average content of group 5 metal is from 5 to 15 at % and the Mo content is ?80 at %. The sputtering target has an average C/O ratio in (at %/at %) of ?1. The sputtering targets can be produced by shaping or forming and have an improved sputtering behavior.

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: An improved interface technique for use in a southbridge or I/O hub or in similar devices is provided where non-posted read requests are received from at least one requestor, and upstream commands based on these requests are transmitted. Response data is received in reply to commands that were previously transmitted, and responses are transmitted to the at least one requester based on the response data. A buffer unit is provided for storing command identification data that identifies commands that were already transmitted or that are still to be transmitted, and response availability data that specifies response data that has been received by the receive engine. The improvement may enable multiple outstanding read requests.

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit is connected to the second circuit unit to send to the second circuit unit request data relating to a request to be sent by the first circuit unit and response data relating to a response to be sent by the first circuit unit over a shared signal line.

Abstract: An interrupt processing technique is provided where an interrupt message is sent to an interrupt controller of a processor in response to an interrupt request from an individual device. The interrupt message comprises a memory address and interrupt status information. The memory address is specifically allocated to the device that has issued the interrupt request. The interrupt status information indicates an interrupt status of the device. An interrupt table that is stored in the memory is updated by the interrupt controller using the interrupt status information comprised in the interrupt message. The interrupt table holds device specific interrupt statuses. Updating the interrupt table comprises addressing the memory using the memory address in the interrupt message.

Abstract: A method an apparatus for providing capability information to a shared controller. In one embodiment, a peripheral bus host controller may be shared by a plurality of peripheral devices coupled to a peripheral bus. The peripheral devices may include coder/decoder (codec) circuitry, and may be implemented using a riser card. The host controller may be configured to query the bus for peripheral devices by reading each address on the bus. During the querying process, the host controller may detect one or more peripheral devices coupled to the bus. Following the completion of the querying of the bus, the host controller may then begin reading configuration information from each of the detected devices. The host controller may employ one or more of several different techniques in order to read configuration information from the peripheral device. The configuration information at a minimum includes a device identifier, which may identify the vendor and the function of the device.

Abstract: An improved interface technology is provided that may be applied to PCI (Peripheral Component Interconnect) devices connected to a southbridge. Requests are received from at least one requestor. The request require responses to be sent back to the respective requestor. The requests are placed by the respective requestor by asserting a request signal, and the request signal is deasserted by the respective requestor when a response is sent back. A retry request may be sent to the current requestor for requesting the current requestor to deassert its request signal although a response has not yet been sent back, and to reassert the request signal later. Together with the retry request, a ready signal is sent indicating whether the request could be processed. This allows the requestor to modify its request when retrying it, if the request was not yet processed.

Abstract: An interrupt processing technique is provided where an interrupt message is sent to an interrupt controller of a processor in response to an interrupt request from an individual device. The interrupt message comprises a memory address and interrupt status information. The memory address is specifically allocated to the device that has issued the interrupt request. The interrupt status information indicates an interrupt status of the device. An interrupt table that is stored in the memory is updated by the interrupt controller using the interrupt status information comprised in the interrupt message. The interrupt table holds device specific interrupt statuses. Updating the interrupt table comprises addressing the memory using the memory address in the interrupt message.

Abstract: An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit is connected to the second circuit unit to send to the second circuit unit request data relating to a request to be sent by the first circuit unit and response data relating to a response to be sent by the first circuit unit over a shared signal line.

Abstract: An improved response reordering technique for use in a southbridge device or I/O hub or similar devices are provided. Non-posted read requests are received from at least one requestor, and upstream commands are transmitted based on the non-posted read requests. Each of the upstream commands is uniquely identified by a command tag. When response data is received in reply to previously transmitted commands, responses are transmitted to the at least one requestor based on the response data. Transmitting the responses comprises reordering the received response data by accessing a buffer of the southbridge device. The buffer stores the received response data and has a plurality of buffer elements that are each uniquely assigned to one of the command tags.

Abstract: An improved interface technology is provided that may be applied to PCI (Peripheral Component Interconnect) devices connected to a southbridge. Requests are received from at least one requestor. The request require responses to be sent back to the respective requestor. The requests are placed by the respective requestor by asserting a request signal, and the request signal is deasserted by the respective requestor when a response is sent back. A retry request may be sent to the current requestor for requesting the current requestor to deassert its request signal although a response has not yet been sent back, and to reassert the request signal later. Together with the retry request, a ready signal is sent indicating whether the request could be processed. This allows the requestor to modify its request when retrying it, if the request was not yet processed.