Abstract: A thin-film solar cell has a rear electrode layer formed of at least 50 atom % of Mo, which in addition to the common contaminants includes 0.1 to 45 atom % of at least one element from the group of Ti, Zr, Hf, V, Nb, Ta, and W, 0 to 7.5 atom % of Na, and 0 to 7.5 atom % of at least one element forming a compound with Na that has a melting point >500 C. The rear electrode layer has good long-term resistance and bonding with the CIGS absorber layer. In addition, the constancy of the alkali metal integration in the absorber layer is improved.

Abstract: An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit is connected to the second circuit unit to send to the second circuit unit request data relating to a request to be sent by the first circuit unit and response data relating to a response to be sent by the first circuit unit over a shared signal line.

Abstract: An interrupt processing technique is provided where an interrupt message is sent to an interrupt controller of a processor in response to an interrupt request from an individual device. The interrupt message comprises a memory address and interrupt status information. The memory address is specifically allocated to the device that has issued the interrupt request. The interrupt status information indicates an interrupt status of the device. An interrupt table that is stored in the memory is updated by the interrupt controller using the interrupt status information comprised in the interrupt message. The interrupt table holds device specific interrupt statuses. Updating the interrupt table comprises addressing the memory using the memory address in the interrupt message.

Abstract: An interrupt handling technique is provided that may allow for sharing level sensitive interrupts in systems where interrupts are message based, i.e., edge triggered. An interrupt input unit is provided for receiving level sensitive interrupt requests and generating request occurrence signals therefrom. An edge detection unit generates start signals for edge triggered interrupt messages on the basis of the request occurrence signals. An interrupt termination detection unit receives termination signals each indicating that an interrupt routine relating to a previous edge triggered interrupt message has terminated. The interrupt input unit is controlled to output a request occurrence signal in response to a received termination signal if a previously received level sensitive interrupt request is still active. That is, a second edge triggered interrupt message may be generated.

Abstract: A method an apparatus for providing capability information to a shared controller. In one embodiment, a peripheral bus host controller may be shared by a plurality of peripheral devices coupled to a peripheral bus. The peripheral devices may include coder/decoder (codec) circuitry, and may be implemented using a riser card. The host controller may be configured to query the bus for peripheral devices by reading each address on the bus. During the querying process, the host controller may detect one or more peripheral devices coupled to the bus. Following the completion of the querying of the bus, the host controller may then begin reading configuration information from each of the detected devices. The host controller may employ one or more of several different techniques in order to read configuration information from the peripheral device. The configuration information at a minimum includes a device identifier, which may identify the vendor and the function of the device.

Abstract: The invention relates to an apparatus and a method for accessing memories having a time-variant response over a PCI bus by using two-stage DMA transfers. The invention provides a method for executing a read request over a PCI bus by transferring the requested data from a main memory of a PCI card to a device located on the PCI bus, comprising the steps of obtaining an access request from a read access queue, transferring, by a first DMA transfer, the requested data from the main memory to a buffer memory on the PCI card, and transferring, by a second DMA transfer, the data from the buffer memory to the device.

Abstract: An improved interface technology is provided that may be applied to PCI (Peripheral Component Interconnect) devices connected to a southbridge. Requests are received from at least one requestor. The request require responses to be sent back to the respective requestor. The requests are placed by the respective requestor by asserting a request signal, and the request signal is deasserted by the respective requestor when a response is sent back. A retry request may be sent to the current requestor for requesting the current requestor to deassert its request signal although a response has not yet been sent back, and to reassert the request signal later. Together with the retry request, a ready signal is sent indicating whether the request could be processed. This allows the requestor to modify its request when retrying it, if the request was not yet processed.

Abstract: An interrupt processing technique is provided where an interrupt message is sent to an interrupt controller of a processor in response to an interrupt request from an individual device. The interrupt message comprises a memory address and interrupt status information. The memory address is specifically allocated to the device that has issued the interrupt request. The interrupt status information indicates an interrupt status of the device. An interrupt table that is stored in the memory is updated by the interrupt controller using the interrupt status information comprised in the interrupt message. The interrupt table holds device specific interrupt statuses. Updating the interrupt table comprises addressing the memory using the memory address in the interrupt message.

Abstract: An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit is connected to the second circuit unit to send to the second circuit unit request data relating to a request to be sent by the first circuit unit and response data relating to a response to be sent by the first circuit unit over a shared signal line.

Abstract: An improved interface technology is provided that may be applied to PCI (Peripheral Component Interconnect) devices connected to a southbridge. Requests are received from at least one requestor. The request require responses to be sent back to the respective requestor. The requests are placed by the respective requestor by asserting a request signal, and the request signal is deasserted by the respective requestor when a response is sent back. A retry request may be sent to the current requestor for requesting the current requestor to deassert its request signal although a response has not yet been sent back, and to reassert the request signal later. Together with the retry request, a ready signal is sent indicating whether the request could be processed. This allows the requestor to modify its request when retrying it, if the request was not yet processed.

Abstract: An improved response reordering technique for use in a southbridge device or I/O hub or similar devices are provided. Non-posted read requests are received from at least one requestor, and upstream commands are transmitted based on the non-posted read requests. Each of the upstream commands is uniquely identified by a command tag. When response data is received in reply to previously transmitted commands, responses are transmitted to the at least one requestor based on the response data. Transmitting the responses comprises reordering the received response data by accessing a buffer of the southbridge device. The buffer stores the received response data and has a plurality of buffer elements that are each uniquely assigned to one of the command tags.

Abstract: An improved interface technique for use in a southbridge or I/O hub or in similar devices is provided where non-posted read requests are received from at least one requestor, and upstream commands based on these requests are transmitted. Response data is received in reply to commands that were previously transmitted, and responses are transmitted to the at least one requester based on the response data. A buffer unit is provided for storing command identification data that identifies commands that were already transmitted or that are still to be transmitted, and response availability data that specifies response data that has been received by the receive engine. The improvement may enable multiple outstanding read requests.

Abstract: A method and apparatus for passing device configuration information to a shared controller. In one embodiment, a host controller may be configured to read configuration from one or more peripheral devices coupled to a serial bus. The peripheral devices may include coder/decoder (codec) circuitry, and may be implemented using a riser card. The host controller may employ one or more of several different techniques in order to read configuration information from the peripheral device. The configuration information at a minimum includes a device identifier, which may identify the vendor and the function of the device. Additional information needed to configure the device to communicate over the peripheral bus may also be obtained with a read of the device, or various lookup mechanisms, such as a lookup table or a tree-like data structure.