Abstract: An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout circuitry, and the readout circuitry provides output signals based on charge or voltage of a storage node. The operating voltage can be selectively provided to each row of a pixel array by a row driver. Each pixel includes a source follower transistor that provides an output signal on a column output line for readout. An anti-blooming transistor may be linked to each pixel's photosensor to provide an overflow path for electrons during charge integration, prior to transfer of charge to the pixel's storage node by a transfer transistor. Electrons not produced by an image are introduced to the photosensor prior to image acquisition, filling traps in the photosensor to reduce image degradation.

Abstract: A pixel cell in which a capacitance is coupled between a storage node and a row select transistor. The pixel cell utilizes a readout timing sequence between operation of a reset transistor and a row select transistor to boost a reset voltage.

Abstract: A rolling shutter technique for a pixel array is described in which multiple rows of the array are hard reset as the shutter moves down the array. As the rolling shutter progresses down the array, each row is hard reset multiple times before its integration period begins, thereby ensuring that the row is in a true hard reset condition at the beginning of its integration period. Also, multiple rows are hard reset in advance of the beginning of the integration period for a given row, thereby making it less likely that overexposed pixels several rows away will be able to distort the integrating row by blooming.

Abstract: A pixel cell in which a capacitance is coupled between a storage node and a row select transistor. The pixel cell utilizes a readout timing sequence between operation of a reset transistor and a row select transistor to boost a reset voltage.

Abstract: A method for automatically measuring the modulation transfer function of an imager is disclosed. A opaque mask is placed over selected columns and rows of the imager during fabrication. In the course of an automated process, photons are uniformly shone over the image sensor. The amount of the input signal that flows from the unmasked pixel cells to the masked pixel cells can then be measured and the modulation transfer function can be determined.

Abstract: A rolling shutter technique for a pixel array is described in which multiple rows of the array are hard reset as the shutter moves down the array. As the rolling shutter progresses down the array, each row is hard reset multiple times before its integration period begins, thereby ensuring that the row is in a true hard reset condition at the beginning of its integration period. Also, multiple rows are hard reset in advance of the beginning of the integration period for a given row, thereby making it less likely that overexposed pixels several rows away will be able to distort the integrating row by blooming.

Abstract: An apparatus and method for fixed pattern noise (FPN) correction in an image sensor utilizes at least one row of test pixels. An external voltage is applied to each pixel circuit in the at least one row. Thus, the output of the test pixels does not depend on the photo or dark current signals. The applied voltage is used to determine a column offset error for each column in the image sensor.

Abstract: The claimed subject matter provides systems and/or methods that facilitate reducing dark current and lag in a CMOS imaging System-on-Chip (iSoC) sensor. For instance, a vertical output driver can output a signal upon a node connected to gates of reset transistors and/or gates of transfer transistors of pixels in the pixel array while operating in rolling shutter mode and/or global shutter mode. Further, a pre-charger can transition a voltage of the node to a first voltage level. Moreover, a booster can further adjust the voltage of the node from the first voltage level to a second voltage level. The booster can have variable drive capability that enables varying operation thereof according to at least one degree of freedom (e.g., speed of the booster proceeding to the second voltage level, frequency of yielding charge to the node, the second voltage level, or timing of the booster and the pre-charger, . . . ).

Abstract: The claimed subject matter provides systems and/or methods that facilitate mitigating an impact resulting from mismatch between signal chains in a CMOS imaging System-on-Chip (iSoC) sensor. Two-by-two pixel structures can be a basic building block upon which a pixel array is constructed. Further, each two-by-two pixel structure can be associated with a read bus that carries a sampled signal to a top end and a bottom end of a chip. Moreover, multiplexers at either end of the chip can select a subset of the read buses from which to receive a subset of the sampled signals. Accordingly, pixels in a first color plane can be read, processed, etc. on the same side of the chip (e.g., utilizing a common signal chain), while pixels in at least one second color plane can be read, processed, etc. on the other side of the chip (e.g., employing a differing signal chain).

Abstract: An anti-eclipse circuit of an image pixel includes a clamping circuit for pulling up a voltage of a reset signal output by the pixel and an eclipse detection circuit for controllably coupling the clamping circuit output to the output of the pixel. The clamping circuit includes a source follower transistor and a switching transistor. The eclipse detection circuit includes a comparator that is operated to detect an eclipse condition. The eclipse detection circuit outputs a control signal to cause the switching transistor to conduct only when a eclipse condition is detected while the pixel is outputting a reset signal.

Abstract: An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout circuitry, and the readout circuitry provides output signals based on charge or voltage of a storage node. The operating voltage can be selectively provided to each row of a pixel array by a row driver. Each pixel includes a source follower transistor that provides an output signal on a column output line for readout. An anti-blooming transistor may be linked to each pixel's photosensor to provide an overflow path for electrons during charge integration, prior to transfer of charge to the pixel's storage node by a transfer transistor. Electrons not produced by an image are introduced to the photosensor prior to image acquisition, filling traps in the photosensor to reduce image degradation.

Abstract: An anti-eclipse circuit of an image pixel includes a clamping circuit for pulling up a voltage of a reset signal output by the pixel and an eclipse detection circuit for controllably coupling the clamping circuit output to the output of the pixel. The clamping circuit includes a source follower transistor and a switching transistor. The eclipse detection circuit includes a comparator that is operated to detect an eclipse condition. The eclipse detection circuit outputs a control signal to cause the switching transistor to conduct only when a eclipse condition is detected while the pixel is outputting a reset signal.

Abstract: A black clamp circuit for an image sensor utilizes a differential programmable gain amplifier and a feed-back loop to adjust a black level based on comparison to a reference black level. The gain (and therefore step size and range) of the feed-back loop constant for all programmable gain amplifier gain settings. The gain of the fee-back loop is kept constant by adjusting the values of programmable capacitors in the circuit.

Abstract: A black clamp stabilization circuit for an image sensor utilizes a mixed-signal SoC block comprising sub-blocks to dynamically and precisely adjust the black level based on comparison to a reference black level. The black level adjustments include a first level regulation using digital control of an analog signal in a feedback loop that includes a programmable gain amplifier and high-resolution A/D converter. By applying the black clamping in the analog domain, dynamic range is extended. Additional black level regulation is subsequently performed in the digital domain to differentially eliminate line noise and column noise generated within the imaging System-on-Chip. By providing information between the sub-blocks, the algorithms can converge more quickly. The technique enables multiple signal paths to separately handle individual colors and to increase imaging data throughput.

Abstract: A pixel cell allows both correlated double sampling (CDS) and automatic light control (ALC) operations through a non-destructive, parallel readout. An image sensor may include an array of pixel cells, some or all of which include a photosensor with two readout circuits attached; peripheral circuitry can sample charges generated from the photosensor through one readout circuit, then perform array readout through the other. One readout circuit connected to the photosensor provides a non-destructive readout of the generated charge. The other readout circuit can, for example, be a multiple-transistor circuit that transfers charge from the photosensor to a floating diffusion node for readout. The image sensor's readout circuitry may thus monitor the light reaching the photosensor of the cell to determine when to read out signals from the entire array.

Abstract: An apparatus and method that reduces the dark current in each pixel of an image sensor, where each pixel has a pinned photodiode. A negative potential barrier at the transfer gate of each pixel is raised when the photodiode is integrating (when the transfer gate is “off”) to thereby eliminate dark current generation in this region. The potential barrier is applied via a “triple well” transistor circuit structure that is capable of handling a strongly negative voltage. The circuit structure also serves as a conduit for conducting a strongly positive voltage to minimize the potential barrier during signal transfer and readout, thereby reducing image lag.

Abstract: A pixel cell allows both correlated double sampling (CDS) and automatic light control (ALC) operations through a non-destructive, parallel readout. An image sensor may include an array of pixel cells, some or all of which include a photosensor with two readout circuits attached; peripheral circuitry can sample charges generated from the photosensor through one readout circuit, then perform array readout through the other. One readout circuit connected to the photosensor provides a non-destructive readout of the generated charge. The other readout circuit can, for example, be a multiple-transistor circuit that transfers charge from the photosensor to a floating diffusion node for readout. The image sensor's readout circuitry may thus monitor the light reaching the photosensor of the cell to determine when to read out signals from the entire array.

Abstract: An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout circuitry, and the readout circuitry provides output signals based on charge or voltage of a storage node. The operating voltage can be selectively provided to each row of a pixel array by a row driver. Each pixel includes a source follower transistor that provides an output signal on a column output line for readout. An anti-blooming transistor may be linked to each pixel's photosensor to provide an overflow path for electrons during charge integration, prior to transfer of charge to the pixel's storage node by a transfer transistor. Electrons not produced by an image are introduced to the photosensor prior to image acquisition, filling traps in the photosensor to reduce image degradation.

Abstract: A method of operating a pixel array includes activating a global storage signal to store a photosensor charge in a first storage region of each pixel, activating a first reset signal for pixels in a first row to reset a second storage region of first row pixels, sampling the reset second storage region, activating a third reset signal for pixels in a second row to reset a third storage region of second row pixels, sampling the reset third storage region, transferring the photosensor charge from the first storage region of pixels in a first set of columns of the first and second rows of the array respectively to the second and third storage regions, sampling the photosensor charge from the second storage region from first row/first column pixels, and sampling the photosensor charge from the third storage region from second row/first column pixels.

Abstract: An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout circuitry, and the readout circuitry provides output signals based on charge or voltage of a storage node. The operating voltage can be selectively provided to each row of a pixel array by a row driver. Each pixel includes a source follower transistor that provides an output signal on a column output line for readout. An anti-blooming transistor may be linked to each pixel's photosensor to provide an overflow path for electrons during charge integration, prior to transfer of charge to the pixel's storage node by a transfer transistor. Electrons not produced by an image are introduced to the photosensor prior to image acquisition, filling traps in the photosensor to reduce image degradation.