Patents by Inventor Johan Bourgeat

Johan Bourgeat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260068326
    Abstract: The present description concerns an electronic device configured to protect an electronic component against electrostatic discharges, the electronic device comprising semiconductor regions extending in depth in a semiconductor substrate from a first surface of the semiconductor substrate, the semiconductor regions comprising a first semiconductor region of a first conductivity type, and comprising a second semiconductor region of the second conductivity type opposite to the first conductivity type, forming a PN junction with the first semiconductor region. The first semiconductor region is coupled to a first conductive track forming a first connection pin of the electronic device, the second semiconductor region is coupled to a second conductive track forming a second connection pin of the electronic device, and the semiconductor substrate is between the first conductive track and the second conductive track.
    Type: Application
    Filed: July 29, 2025
    Publication date: March 5, 2026
    Inventors: Chloe Troussier, Johan Bourgeat
  • Patent number: 12538583
    Abstract: An electronic device includes a doped semiconductor substrate of a first conductivity type. First and second doped wells are provided, separated from each other by trench isolation, within the doped semiconductor substrate. At least one first region and at least one second region are respectively located in the first and second doped wells, with each first and second region having a doping level higher than a doping level of the first and second doped wells. The trench isolation penetrates into the first and second doped wells and extends laterally between the first region and second region. A third region laterally extends between the first and second doped wells at a location under the insulating trench. The third region has a doping level lower than the doping level of the first and second doped wells.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: January 27, 2026
    Assignee: STMicroelectronics France
    Inventors: Yohann Solaro, Johan Bourgeat
  • Publication number: 20250081627
    Abstract: An ESD protection device includes at least one semiconductor electronic switch electrically coupled in parallel with a diode. The semiconductor electronic switch and the diode each include at least one finger extending substantially parallel to a first direction. The fingers of the semiconductor electronic switch and of the diode are aligned with each other along this first direction.
    Type: Application
    Filed: August 29, 2024
    Publication date: March 6, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Chloe TROUSSIER, Johan BOURGEAT
  • Publication number: 20240072037
    Abstract: An electronic device includes a doped semiconductor substrate of a first conductivity type. A first doped well of a second conductivity type opposite to the first conductivity type extends into the doped semiconductor substrate from a surface thereof. A second doped well of the first conductivity type is located in the first well. A third electrically-insulating well is located in the second well. A fourth doped well of the first conductivity type is located in the third well. First, second, and third doped regions of the first conductivity type are respectively located in the doped semiconductor substrate, the second doped well and the fourth doped well. The first, second, and third doped regions have doping levels greater than a doping level of the doped semiconductor substrate. A fourth doped region the second conductivity type is located in the fourth doped well adjacent the second doped region.
    Type: Application
    Filed: August 9, 2023
    Publication date: February 29, 2024
    Applicant: STMicroelectronics SA
    Inventors: Johan BOURGEAT, Yohann SOLARO
  • Publication number: 20240072036
    Abstract: An electronic device includes a doped semiconductor substrate of a first conductivity type. First and second doped wells are provided, separated from each other by trench isolation, within the doped semiconductor substrate. At least one first region and at least one second region are respectively located in the first and second doped wells, with each first and second region having a doping level higher than a doping level of the first and second doped wells. The trench isolation penetrates into the first and second doped wells and extends laterally between the first region and second region. A third region laterally extends between the first and second doped wells at a location under the insulating trench. The third region has a doping level lower than the doping level of the first and second doped wells.
    Type: Application
    Filed: August 9, 2023
    Publication date: February 29, 2024
    Applicant: STMicroelectronics SA
    Inventors: Yohann SOLARO, Johan BOURGEAT
  • Patent number: 11887982
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: January 30, 2024
    Assignee: STMicroelectronics SA
    Inventor: Johan Bourgeat
  • Patent number: 11444077
    Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: September 13, 2022
    Assignee: STMicroelectronics SA
    Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
  • Publication number: 20210193648
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Application
    Filed: March 3, 2021
    Publication date: June 24, 2021
    Applicant: STMicroelectronics SA
    Inventor: Johan BOURGEAT
  • Patent number: 10971489
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: April 6, 2021
    Assignee: STMicroelectronics SA
    Inventor: Johan Bourgeat
  • Publication number: 20200098743
    Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
  • Patent number: 10515946
    Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 24, 2019
    Assignee: STMicroelectronics SA
    Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
  • Publication number: 20190267367
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Application
    Filed: May 8, 2019
    Publication date: August 29, 2019
    Applicant: STMicroelectronics SA
    Inventor: Johan BOURGEAT
  • Patent number: 10340265
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: July 2, 2019
    Assignee: STMicroelectronics SA
    Inventor: Johan Bourgeat
  • Publication number: 20180269199
    Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
  • Publication number: 20180254270
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Application
    Filed: September 1, 2017
    Publication date: September 6, 2018
    Applicant: STMicroelectronics SA
    Inventor: Johan Bourgeat
  • Patent number: 9997512
    Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 12, 2018
    Assignee: STMicroelectronics SA
    Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
  • Patent number: 9997907
    Abstract: An electronic device includes first and second terminals with an electronic circuit coupled there between. The electronic circuit includes a protection circuit and a resistive-capacitive circuit. The resistive-capacitive circuit triggers the protection circuit to protect against electrostatic discharges in the presence of a current pulse between the first and second terminals. A control circuit is configured to slow down a discharge from the resistive-capacitive circuit when the protection circuit is triggered.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: June 12, 2018
    Assignee: STMicroelectronics SA
    Inventors: Johan Bourgeat, Boris Heitz, Jean Jimenez
  • Patent number: 9991173
    Abstract: An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate, thyristors coupled in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1. Each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of a transistor to be protected, and produced in the CMOS technology.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: June 5, 2018
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Johan Bourgeat
  • Publication number: 20180130788
    Abstract: An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.
    Type: Application
    Filed: January 5, 2018
    Publication date: May 10, 2018
    Applicant: STMicroelectronics SA
    Inventors: Johan Bourgeat, Jean Jimenez
  • Patent number: 9899366
    Abstract: An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: February 20, 2018
    Assignee: STMicroelectronics SA
    Inventors: Johan Bourgeat, Jean Jimenez