Patents by Inventor Johan Bourgeat
Johan Bourgeat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160315077Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.Type: ApplicationFiled: June 30, 2016Publication date: October 27, 2016Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
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Patent number: 9401351Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.Type: GrantFiled: January 30, 2015Date of Patent: July 26, 2016Assignee: STMicroelectronics SAInventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
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Patent number: 9299668Abstract: A device for protecting a set of N nodes from electrostatic discharges, wherein N is greater than or equal to three, includes a set of N units respectively possessing N first terminals respectively connected to the N nodes and N second terminals connected together to form a common terminal. Each unit includes at least one MOS transistor including a parasitic transistor connected between a pair of the N nodes and configured, in the presence of a current pulse between the pair of nodes, to operate, at least temporarily, in a hybrid mode including MOS-type operation in a sub-threshold mode and operation of the bipolar transistor.Type: GrantFiled: December 5, 2012Date of Patent: March 29, 2016Assignee: STMicroelectronics SAInventors: Johan Bourgeat, Philippe Galy
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Patent number: 9287254Abstract: An electronic device includes a first device terminal and a second device terminal. A first and a second thyristor are reverse-connected between the two device terminals. A first and a second MOS transistor are respectively coupled between the conduction electrodes (emitters and collectors) of the two NPN transistors of the two thyristors. A third MOS transistor is coupled between the emitters of the two NPN bipolar transistors of the two thyristors and a fourth MOS transistor is coupled between the bases of the two PNP bipolar transistors of the two thyristors. A gate region is common to all the MOS transistors and a semiconductor substrate region includes the substrates of all the MOS transistors.Type: GrantFiled: January 16, 2015Date of Patent: March 15, 2016Assignee: STMicroelectronics S.A.Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat
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Publication number: 20150214210Abstract: An electronic device includes a first device terminal and a second device terminal. A first and a second thyristor are reverse-connected between the two device terminals. A first and a second MOS transistor are respectively coupled between the conduction electrodes (emitters and collectors) of the two NPN transistors of the two thyristors. A third MOS transistor is coupled between the emitters of the two NPN bipolar transistors of the two thyristors and a fourth MOS transistor is coupled between the bases of the two PNP bipolar transistors of the two thyristors.Type: ApplicationFiled: January 16, 2015Publication date: July 30, 2015Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat
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Publication number: 20150214214Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.Type: ApplicationFiled: January 30, 2015Publication date: July 30, 2015Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
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Patent number: 9019666Abstract: The electronic device includes a first (BP) and a second (BN) terminal and electronic means coupled between said two terminals; the electronic means include at least one block (BLC) comprising an MOS transistor (TR) including a parasitic bipolar transistor, the MOS transistor having the drain (D) thereof coupled to the first terminal (BP), the source (S) thereof coupled to the second terminal (BN) and being additionally configured, in the event of a current pulse (IMP) between the two terminals, to operate in a hybrid mode including MOS operation in a subthreshold mode and operation of the parasitic bipolar transistor. The device can comprise two blocks (BLC1, BLC2) connected symmetrically between the two terminals (BP, BN) with a triac (TRC) the trigger of which is connected to the common terminal (BC) of the two blocks.Type: GrantFiled: January 20, 2011Date of Patent: April 28, 2015Assignee: STMicroelectronics S.A.Inventors: Johan Bourgeat, Christophe Entringer, Philippe Galy, Jean Jimenez
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Publication number: 20150077888Abstract: A device includes a transistor configured for operating in a hybrid mode, an element configured for generating and injecting a current into the substrate of the transistor in the presence of an ESD pulse, and a thyristor triggerable at least by the element.Type: ApplicationFiled: September 3, 2014Publication date: March 19, 2015Inventors: Philippe Galy, Johan Bourgeat
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Patent number: 8937334Abstract: A triggerable bidirectional semiconductor device has two terminals and at least one gate. The device comprises, within a layer of silicon on insulator, a central semiconductor zone incorporating the at least one gate and comprising a central region having a first conductivity type, two intermediate regions having a second conductivity type respectively arranged on either side of and in contact with the central region, two semiconductor end zones respectively arranged on either side of the central zone, each end zone comprising two end regions having opposite types of conductivity, in contact with the adjacent intermediate region, the two end regions of each end zone being mutually connected electrically in order to form the two terminals of the device.Type: GrantFiled: June 14, 2012Date of Patent: January 20, 2015Assignee: STMicroelectronics SAInventors: Thomas Benoist, Philippe Galy, Johan Bourgeat, Frank Jezequel, Nicolas Guitard
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Patent number: 8907373Abstract: A protection device includes a triac and triggering units. Each triggering unit is formed by a MOS transistor configured to operate at least temporarily in a hybrid operating mode and a field-effect diode. The field-effect diode has a controlled gate that is connected to the gate of the MOS transistor.Type: GrantFiled: September 27, 2012Date of Patent: December 9, 2014Assignee: STMicroelectronics SAInventors: Philippe Galy, Jean Jimenez, Johan Bourgeat, Boris Heitz
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Publication number: 20140197448Abstract: An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1. Each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of a transistor to be protected, and produced in the CMOS technology.Type: ApplicationFiled: January 15, 2014Publication date: July 17, 2014Applicant: STMICROELECTRONICS SAInventors: Philippe Galy, Johan Bourgeat
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Patent number: 8598938Abstract: A power switch includes first and second MOS transistors in series between first and second nodes. Both the first and second transistors have a gate coupled to its substrate. First and second resistive elements are coupled between the gate of the first transistor and the first node, and between the gate of the second transistor and the second node, respectively. A triac is coupled between the first and second nodes. The gate of the triac is coupled to a third node common to the first and second transistors. A third MOS transistor has a first conduction electrode coupled to the gate of the first transistor and a second conduction electrode coupled to the gate of the second transistor.Type: GrantFiled: November 1, 2012Date of Patent: December 3, 2013Assignee: STMicroelectronics SAInventors: Philippe Galy, Johan Bourgeat
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Publication number: 20130141824Abstract: The electronic device includes a first (BP) and a second (BN) terminal and electronic means coupled between said two terminals; the electronic means include at least one block (BLC) comprising an MOS transistor (TR) including a parasitic bipolar transistor, the MOS transistor having the drain (D) thereof coupled to the first terminal (BP), the source (S) thereof coupled to the second terminal (BN) and being additionally configured, in the event of a current pulse (IMP) between the two terminals, to operate in a hybrid mode including MOS operation in a subthreshold mode and operation of the parasitic bipolar transistor. The device can comprise two blocks (BLC1, BLC2) connected symmetrically between the two terminals (BP, BN) with a triac (TRC) the trigger of which is connected to the common terminal (BC) of the two blocks.Type: ApplicationFiled: January 20, 2011Publication date: June 6, 2013Applicants: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, STMICROELECTRONICS SAInventors: Johan Bourgeat, Christophe Entringer, Philippe Galy, Jean Jimenez
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Publication number: 20120319204Abstract: A triggerable bidirectional semiconductor device has two terminals and at least one gate. The device comprises, within a layer of silicon on insulator, a central semiconductor zone incorporating the at least one gate and comprising a central region having a first conductivity type, two intermediate regions having a second conductivity type respectively arranged on either side of and in contact with the central region, two semiconductor end zones respectively arranged on either side of the central zone, each end zone comprising two end regions having opposite types of conductivity, in contact with the adjacent intermediate region, the two end regions of each end zone being mutually connected electrically in order to form the two terminals of the device.Type: ApplicationFiled: June 14, 2012Publication date: December 20, 2012Applicant: STMICROELECTRONICS SAInventors: Thomas Benoist, Philippe Galy, Johan Bourgeat, Frank Jezequel, Nicolas Guitard
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Patent number: 8331069Abstract: A structure for protecting an integrated circuit against electrostatic discharges, comprising an assembly of identical cells, each of which is connected to a terminal forming a pad of the circuit, a first supply rail, or a second supply rail, the cells forming between any two of said terminals an assembly of four alternated layers of different conductivity types.Type: GrantFiled: April 14, 2010Date of Patent: December 11, 2012Assignee: STMicroelectronics SAInventors: Philippe Galy, Christophe Entringer, Johan Bourgeat
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Publication number: 20120275075Abstract: Semiconducting device for protecting at least one node of an integrated circuit against electrostatic discharges, comprising a doublet of floating gate thyristors connected in parallel and head-to-foot, the two thyristors having respectively two distinct gates and a common gate formed by a common semiconducting layer, the anode of a first thyristor of the doublet and the cathode of the second thyristor of the doublet forming a first terminal of the doublet designed to be connected to a cold point and the cathode of the first thyristor of the doublet and the anode of the second thyristor of the doublet forming a second terminal of the doublet designed to be connected to the said node to be protected.Type: ApplicationFiled: April 26, 2012Publication date: November 1, 2012Applicant: STMicroelectronics SAInventors: Alexandre Dray, Philippe Galy, Johan Bourgeat
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Publication number: 20100271741Abstract: A structure for protecting an integrated circuit against electrostatic discharges, comprising an assembly of identical cells, each of which is connected to a terminal forming a pad of the circuit, a first supply rail, or a second supply rail, the cells forming between any two of said terminals an assembly of four alternated layers of different conductivity types.Type: ApplicationFiled: April 14, 2010Publication date: October 28, 2010Inventors: Philippe Galy, Christophe Entringer, Johan Bourgeat