Abstract: A non-integer decimation filter for decimating an input value includes a first integrator for integrating the input value in an input sample domain at an input sample rate and for generating a first integral of the input value at its output and a second integrator for integrating the first integral of the input value in the input sample domain at the input sample rate and for generating a second integral at its output. A calculation network is coupled to the outputs of the first and second integrators for combining the outputs of the first and second integrators with corresponding coefficients to generate intermediate output values in an output sample domain. A differentiator is configured to receive the intermediate output values from the calculation network and to generate a decimated output value at an output sample rate in which the output sample rate has a non-integer factor with respect to the input sample rate.

Abstract: An output driver circuit including a transistor for pulling down an output terminal voltage and a charge pump for driving an input of the transistor to pull-down the output terminal voltage substantially to zero volts in response to a selected level of an input signal.

Abstract: A single-ended, non-differential switched capacitor circuit is disclosed which removes the effect of common mode noise. To this end, the circuit creates a capacitance divider using the sampling capacitors, Cs, to create a stable and noise-free common mode voltage (Vcom) signal. Once created, this Vcom signal is coupled across a large common mode capacitance, Ccom, which is preferably off chip, to further control its value. Thereafter, the voltage Vcom is preferably allowed to settle while the data is disconnected. In this way, the Vcom signal is not provided to the circuit, but instead is cleanly generated within the circuit itself when needed. Thereafter, the generated Vcom signal is paralleled with the integration capacitor, C1, to produce the non-differential output voltage Vout. Then, the sampling capacitors, Cs, are shorted to remove any charges stored on them and the process is repeated.

Abstract: Signal processing systems described herein include an analog-to-digital delta sigma modulator to process a single-ended input signal using a single-ended analog feedback reference signal. The delta sigma modulator includes a switched capacitor circuit that integrates a difference between the single-ended input signal and the single-ended analog feedback signal derived from a quantization output of the delta sigma modulator. Embodiments of the switched capacitor circuit allow the delta sigma modulator to be implemented with fewer switches, less complicated reference signal generators, and smaller capacitors relative to conventional counterparts. Thus, embodiments of the delta sigma modulator described herein can cost less to build and use less power. Embodiments of the signal processing systems can be implemented in single and multi-bit delta sigma modulators and various sampling topologies, including single and double sampling topologies.

Abstract: A digital to analog converter including an input for receiving an input signal, a ramp generator, and a delta-sigma modulator responsive to the input signal and an output of the ramp generator. An order of a noise shaping transfer function of the delta-sigma modulator is response to a level of the output of the ramp generator.