Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a photonic receiver; and a die coupled to the photonic receiver by interconnects, wherein the die comprises a device layer between a first interconnect layer of the die and a second interconnect layer of the die. In still some embodiments, a microelectronic assembly may include a photonic transmitter; and a die coupled to the photonic transmitter by interconnects, wherein the die comprises a device layer between a first interconnect layer of the die and a second interconnect layer of the die.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a transmitter/receiver logic (TRL) die coupled to the first surface of the package substrate; a plurality of antenna elements adjacent the second surface of the package substrate; and a transmitter/receiver chain (TRC) die, wherein the TRC die is embedded in the package substrate, and wherein the TRC die is electrically coupled to the RF die and at least one of the plurality of antenna elements via conductive pathways in the package substrate. In some embodiments, a microelectronic assembly may further include a double-sided TRC die. In some embodiments, a microelectronic assembly may further include a TRC die having an amplifier. In some embodiments, a microelectronic assembly may further include a TRL die having a modem and a phase shifter.

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

Abstract: Embodiments of the invention include an acoustic wave resonator (AWR) module. In an embodiment, the AWR module may include a first AWR substrate and a second AWR substrate affixed to the first AWR substrate. In an embodiment, the first AWR substrate and the second AWR substrate define a hermetically sealed cavity. A first AWR device may be positioned in the cavity and formed on the first AWR substrate, and a second AWR device may be positioned in the cavity and formed on the second AWR substrate. In an embodiment, a center frequency of the first AWR device is different than a center frequency of the second AWR device. In additional embodiment of the invention, the AWR module may be integrated into a hybrid filter. The hybrid filter may include an AWR module and other RF passive devices embedded in a packaging substrate.

Abstract: Embodiments include devices and methods, including a method for processing a substrate. The method includes providing a substrate including a first portion and a second portion, the first portion including a feature, the feature including an electrically conductive region, the second portion including a dielectric surface region. The method also includes performing self-assembled monolayer (SAM) assisted structuring plating to form a structure comprising a metal on the dielectric surface region, the feature being formed using a process other than the SAM assisted structuring plating used to form the structure, and the structure being formed after the feature. Other embodiments are described and claimed.

Abstract: Packaged RF front end systems including a hybrid filter and an active circuit in a single package are described. In an example, a package includes an active die comprising an acoustic wave resonator. A package substrate is electrically coupled to the active die. A seal frame surrounds the acoustic wave resonator and is attached to the active die and to the package substrate, the seal frame hermetically sealing the acoustic wave resonator in a cavity between the active die and the package substrate.

Abstract: A device package and a method of forming the device package are described. The device package includes one or more dies disposed on a first substrate. The device packages further includes one or more interconnects vertically disposed on the first substrate, and a mold layer disposed over and around the first die, the one or more interconnects, and the first substrate. The device package has a second die disposed on a second substrate, wherein the first substrate is electrically coupled to the second substrate with the one or more interconnects, and wherein the one or more interconnects are directly disposed on at least one of a top surface of the first substrate and a bottom surface of the second substrate without an adhesive layer. The device package may include one or more interconnects having one or more different thicknesses or heights at different locations on the first substrate.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.

Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Abstract: RF front end systems or modules with an acoustic wave resonator (AWR) on an interposer substrate are described. In an example, an integrated system includes an active die, the active die comprising a semiconductor substrate having a plurality of active circuits therein. An interposer is also included, the interposer comprising an acoustic wave resonator (AWR). A seal frame couples the active die to the interposer, the seal frame surrounding the acoustic wave resonator and hermetically sealing the acoustic wave resonator between the active die and the interposer.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first photodefinable material on at least a portion of the second surface, and a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Abstract: A device package has substrates disposed on top of one another to form a stack, and pads formed on at least one of the top surface and the bottom surface of each of the substrates. The device package has interconnects electrically coupling at least one of the top surface and the bottom surface of each substrate to at least one of the top surface and the bottom surface of another substrate. The device package has pillars disposed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. The device package also has adhesive layers formed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates.

Abstract: A device package and a method of forming a device package are described. The device package includes a plurality of posts disposed on a substrate. Each post has a top surface and a bottom surface that is opposite from the top surface. The device package also has one or more dies disposed on the substrate. The dies are adjacent to the plurality of posts on the substrate. The device package further includes a lid disposed above the plurality of posts and the one or more dies on the substrate. The lid has a top surface and a bottom surface that is opposite from the top surface. Lastly, an adhesive layer attaches the top surfaces of the plurality of posts and the bottom surface of the lid. The device package may also include one or more thermal interface materials (TIMs) disposed on the dies.