Patents by Inventor Johannes Adrianus Maria De Boet

Johannes Adrianus Maria De Boet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240080003
    Abstract: Example embodiments relate to digital RF amplifiers. One example digital RF amplifier includes a driver having a plurality of outputs and being configured to individually set a signal level at the outputs either to an inactive or active level in response to a digital input signal. The RF amplifier also includes a transistor configured to output an analog RF signal at a transistor output. The transistor includes a plurality of transistor cells, each including a control terminal, an output terminal, and a common terminal. The transistor also includes a plurality of transistor inputs, each transistor input being electrically connected to the control terminal of at least one transistor cell. The transistor inputs are mutually electrically isolated. Each transistor input is connected to a different output of the driver. The transistor output is electrically connected to the output terminals of the plurality of transistor cells. The transistor is a circular transistor.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 7, 2024
    Inventors: Johannes Adrianus Maria De Boet, Daniel Maassen, Rob Mathijs Heeres
  • Publication number: 20210336025
    Abstract: Example embodiments relate to field-effect transistors. An example field-effect transistor includes a plurality of field-effect transistor elements, each field-effect transistor element including a gate finger and a gate runner. The gate finger of each field-effect transistor element is electrically connected at a plurality of spaced apart positions to the gate runner of that element. Each gate finger is made of a first material or material composition and has a first electrical resistivity. The field-effect transistor further includes, for each gate finger, a gate resistor through which the electrical connection between the gate finger and the gate runner at a position among the plurality of spaced apart positions is realized. The gate resistor is made of a second material or material composition and has a second electrical resistivity that is higher than the first electrical resistivity.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 28, 2021
    Inventor: Johannes Adrianus Maria De Boet
  • Patent number: 10685927
    Abstract: A packaged RF power amplifier comprises an output network coupled to the output of a RF power transistor, which output network comprises a plurality of first bondwires extending along a first direction between the output of transistor and an output lead of the package, a series connection of a second inductor and a first capacitor between the output of the RF power transistor and ground, and a series connection of a third inductor and a second capacitor connected in between ground and the junction between the second inductor and the first capacitor. The first and second capacitors are integrated on a single passive die and the third inductor comprises a first part and a second part connected in series, wherein the first part extends at least partially along the first direction, and wherein the second part extends at least partially in a direction opposite to the first direction.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: June 16, 2020
    Assignee: Ampleon Netherlands B.V.
    Inventors: Johannes Adrianus Maria De Boet, Yi Zhu, Yuri Volokhine, Vittorio Cuoco, Albertus Gerardus Wilhelmus Philipus Van Zuijlen, Iordan Konstantlnov Sveshtarov, Josephus Henricus Bartholomeus Van der Zanden
  • Patent number: 10453810
    Abstract: The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 22, 2019
    Assignee: Ampleon Netherlands B.V.
    Inventors: Johannes Adrianus Maria De Boet, Freerk Van Rijs, Iordan Konstantinov Sveshtarov
  • Publication number: 20190229077
    Abstract: A packaged RF power amplifier comprises an output network coupled to the output of a RF power transistor, which output network comprises a plurality of first bondwires extending along a first direction between the output of transistor and an output lead of the package, a series connection of a second inductor and a first capacitor between the output of the RF power transistor and ground, and a series connection of a third inductor and a second capacitor connected in between ground and the junction between the second inductor and the first capacitor. The first and second capacitors are integrated on a single passive die and the third inductor comprises a first part and a second part connected in series, wherein the first part extends at least partially along the first direction, and wherein the second part extends at least partially in a direction opposite to the first direction.
    Type: Application
    Filed: August 23, 2017
    Publication date: July 25, 2019
    Inventors: Johannes Adrianus Maria De Boet, Yi Zhu, Yuri Volokhine, Vittorio Cuoco, Albertus Gerardus Wihelmusi Van Zuijlen, Jordan Konstantlnov Sveshtarov
  • Publication number: 20190172804
    Abstract: The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.
    Type: Application
    Filed: January 29, 2019
    Publication date: June 6, 2019
    Applicant: Ampleon Netherlands B.V.
    Inventors: Johannes Adrianus Maria De Boet, Freerk Van Rijs, Iordan Konstantinov Sveshtarov
  • Patent number: 10242960
    Abstract: The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: March 26, 2019
    Assignee: Ampleon Netherlands B.V.
    Inventors: Johannes Adrianus Maria De Boet, Freerk Van Rijs, Iordan Konstantinov Sveshtarov
  • Publication number: 20180026000
    Abstract: The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.
    Type: Application
    Filed: July 20, 2017
    Publication date: January 25, 2018
    Applicant: Ampleon Netherlands B.V.
    Inventors: Johannes Adrianus Maria De Boet, Freerk Van Rijs, Iordan Konstantinov Sveshtarov
  • Publication number: 20170085229
    Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface. the device also includes a gate located on the major surface. The device further includes a drain region having a first conductivity type. The device also includes a source region having the first conductivity type, wherein the source region is located within a region having a second conductivity type. The device further includes a channel region comprised of a part of the region having the second conductivity type that is located beneath the gate. The drain region extends laterally away from the gate along the major surface of the substrate. The drain also extends beneath the gate, the source region and the region having the second conductivity type to isolate the source region and the region having the second conductivity type from an underlying region of the substrate.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 23, 2017
    Inventor: Johannes Adrianus Maria De Boet
  • Patent number: 9019671
    Abstract: The invention relates to an electronic device comprising an RF-LDMOS transistor (1) and a protection circuit (2) for the RF-LDMOS transistor. The protection circuit (2) comprises: i) an input terminal (Ni) coupled to a drain terminal (Drn) of the RF-LDMOS transistor (1); ii) a clipping node (Nc); iii) a clipping circuit (3) coupled to the clipping node (Nc) for substantially keeping the voltage on the clipping node (Nc) below a predefined reference voltage, wherein the predefined reference voltage is designed to be larger than the operation voltage on the drain terminal (Drn) and lower than a trigger voltage of a parasitic bipolar transistor (100) that is inherently present in the RF-LDMOS transistor; iv) a capacitance (Ct) coupled between the clipping node (Nc) and a further reference voltage terminal (Gnd), and v) a rectifying element (D1, D2) connected with its anode terminal to the input terminal (Ni) and with its cathode terminal to the clipping node (Nc).
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: April 28, 2015
    Assignee: NXP, B.V.
    Inventor: Johannes Adrianus Maria De Boet
  • Patent number: 8891214
    Abstract: Disclosed is a circuit (100) comprising a transistor (110) coupled between a supply voltage line (102) and ground (106), the transistor comprising a control terminal coupled to a input signal line (104), the circuit further comprising first and second bipolar transistors (122, 124) coupled in series between the input signal line (104) and ground (106), wherein the base of the first bipolar transistor is connected to the input signal line and the base of the second bipolar transistor is connected to ground.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: November 18, 2014
    Assignee: NXP, B.V.
    Inventor: Johannes Adrianus Maria de Boet
  • Publication number: 20130307055
    Abstract: The invention relates to an electronic device comprising an RF-LDMOS transistor (1) and a protection circuit (2) for the RF-LDMOS transistor. The protection circuit (2) comprises: i) an input terminal (Ni) coupled to a drain terminal (Drn) of the RF-LDMOS transistor (1); ii) a clipping node (Nc); iii) a clipping circuit (3) coupled to the clipping node (Nc) for substantially keeping the voltage on the clipping node (Nc) below a predefined reference voltage, wherein the predefined reference voltage is designed to be larger than the operation voltage on the drain terminal (Drn) and lower than a trigger voltage of a parasitic bipolar transistor (100) that is inherently present in the RF-LDMOS transistor; iv) a capacitance (Ct) coupled between the clipping node (Nc) and a further reference voltage terminal (Gnd), and v) a rectifying element (D1, D2) connected with its anode terminal to the input terminal (Ni) and with its cathode terminal to the clipping node (Nc).
    Type: Application
    Filed: May 3, 2013
    Publication date: November 21, 2013
    Applicant: NXP B.V.
    Inventor: Johannes Adrianus Maria De Boet
  • Patent number: 8450802
    Abstract: Laterally diffused metal oxide semiconductor transistor for a radio frequency-power: amplifier comprising a drain finger (25,27) which drain finger is connected to a stack of one or more metal interconnect layers, (123,61,59,125) wherein a metal interconnect layer (123) of said stack is connected to a drain region (25) on the substrate, wherein said stack comprises a field plate (123, 125, 121) adapted to reduce the maximum magnitude of the electric field between the drain and the substrate and overlying the tip of said drain finger.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: May 28, 2013
    Assignee: NXP B.V.
    Inventors: Johannes Adrianus Maria De Boet, Henk Jan Peuscher, Paul Bron, Stephan Jo Cecile Henri Theeuwen
  • Publication number: 20130107403
    Abstract: Disclosed is a circuit (100) comprising a transistor (110) coupled between a supply voltage line (102) and ground (106), the transistor comprising a control terminal coupled to a input signal line (104), the circuit further comprising first and second bipolar transistors (122, 124) coupled in series between the input signal line (104) and ground (106), wherein the base of the first bipolar transistor is connected to the input signal line and the base of the second bipolar transistor is connected to ground.
    Type: Application
    Filed: April 19, 2012
    Publication date: May 2, 2013
    Applicant: NXP B.V.
    Inventor: Johannes Adrianus Maria de Boet
  • Publication number: 20110121389
    Abstract: Laterally diffused metal oxide semiconductor transistor for a radio frequency-power: amplifier comprising a drain finger (25,27) which drain finger is connected to a stack of one or more metal interconnect layers, (123,61,59,125) wherein a metal interconnect layer (123) of said stack is connected to a drain region (25) on the substrate, wherein said stack comprises a field plate (123, 125, 121) adapted to reduce the maximum magnitude of the electric field between the drain and the substrate and overlying the tip of said drain finger.
    Type: Application
    Filed: July 20, 2009
    Publication date: May 26, 2011
    Applicant: NXP B.V.
    Inventors: Johannes Adrianus Maria De Boet, Henk Jan Peuscher, Paul Bron, Stephan Jo Cecile Henri Theeuwen
  • Patent number: 7576387
    Abstract: The MOS transistor (1) of the invention comprises a gate electrode (10), a channel region (4), a drain contact region (6) and a drain extension region (7) mutually connecting the channel region (4) and the drain contact region (6). The MOS transistor (1) further comprises a shield layer (11) which extends over the drain extension region (7) wherein the distance between the shield layer (11) and the drain extension region (7) increases in a direction from the gate electrode (10) towards the drain contact region (6). In this way the lateral breakdown voltage of the MOS transistor (1) is increased to a level at which the MOS transistor (1) may fulfill the ruggedness requirement for broadcast applications for a supply voltage higher than that used in base station applications.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: August 18, 2009
    Assignee: NXP B.V.
    Inventors: Stephan Jo Cecil Henri Theeuwen, Johannes Adrianus Maria De Boet, Jos Gerjan Eusebius Klappe
  • Publication number: 20080308862
    Abstract: The MOS transistor (1) of the invention comprises a gate electrode (10), a channel region (4), a drain contact region (6) and a drain extension region (7) mutually connecting the channel region (4) and the drain contact region (6). The MOS transistor (1) further comprises a shield layer (11) which extends over the drain extension region (7) wherein the distance between the shield layer (11) and the drain extension region (7) increases in a direction from the gate electrode (10) towards the drain contact region (6). In this way the lateral breakdown voltage of the MOS transistor (1) is increased to a level at which the MOS transistor (1) may fulfill the ruggedness requirement for broadcast applications for a supply voltage higher than that used in base station applications.
    Type: Application
    Filed: December 12, 2006
    Publication date: December 18, 2008
    Applicant: NXP B.V.
    Inventors: Stephan Jo Cecile Henri Theeuwen, Johannes Adrianus Maria De Boet, Johannes Gerjan Eusebius Klappe