Abstract: The invention relates to frequency conversion systems, in particular for use as up-converters or down-converters in radiofrequency (RF) receivers or transmitters, exemplary embodiments including a radiofrequency receiver (1000) comprising: an RF signal input (1001); a mixing module (1002) comprising a first plurality of IF amplifiers (10041-3) each connected to the RF signal input (1001) via a switch (10031-3); a multi-phase local oscillator signal generator (1300) configured to provide a switching signal to each switch (10031-3); and a summing module (1005) configured to receive output signals from each of the IF amplifiers (10041-3) and to provide a second plurality of output IF signals from a weighted sum of the IF amplifier output signals, wherein the second plurality is different to the first plurality.

Abstract: The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and a plurality of input lines connected to respective output lines (203) of the bit sequence generator (201) and a clock signal input line (205), wherein the digital signal generator (202) is configured to provide an output bit sequence on the serial output line (204) at a rate given by a clock signal provided on the clock signal input line (205) and a sequence given by a sequence of bits from the bit sequence generator (201) on the plurality of input lines (203).

Abstract: A tuning method and tuner apparatus having a plurality of frequency conversion stages for concurrently receiving more than one channel. To avoid disturbance by oscillator pulling, a multi-phased local oscillator signal required by sub-mixers of a DAC mixer share the same timing reference. To minimize the complexity, die area and power dissipation of the local oscillation generation, a tuning offset is accepted from each of the down-conversion stages, and loss of receiver performance by the tuning offset is avoided by a control function for controlling the receiver circuit to process an increased dynamic range introduced by the tuning offset.

Abstract: A signal processing arrangement comprises an amplifier (AMP V1) that includes a stage with complementary transistors (MP3, MN3) of opposite conductivity type arranged in series between two supply lines (+, ?). A controllable biasing circuit (CCS) is provided for changing a quiescent operating point of the stage as a function of a control signal (CS). A control arrangement measures an even order 5 distortion of the amplifier (AMP V1) and adjusts the control signal (CS) so that the even order distortion is below a critical level.

Abstract: A signal processing arrangement comprises a series of latches (XDL, L1, L2) arranged as a clocked delay line (CDL) having a data input and a data output that are coupled to each other so as to form an inverting loop. An enable circuit (ACDL) allows or prevents a latch (L2) in the series of latches from changing state depending on whether, one clock cycle ago, the latch concerned received a given binary value or the inverse of that given binary 5 value, respectively, from the preceding latch (L1) in the series of latches. Such a circuit configuration allows a low-cost frequency division by an odd number with relatively small duty cycle errors.

Abstract: A frequency conversion circuit configured to mix a first input signal (RF+,RF?) at a first frequency with a second input signal (LO+,LO?) at a second frequency to provide an output intermediate frequency signal (IFout), the circuit comprising: first and second mixing modules , each mixing module comprising a voltage to current converter configured to receive the first input signal (RF+,RF?) and connected to a Gilbert mixer configured to receive the second input signal (LO+,LO?); an intermediate frequency output circuit having inputs connected to receive an intermediate frequency current signal (IF+,IF?) from outputs of each of the Gilbert mixers and an output configured to provide the output intermediate frequency voltage signal (IFout), wherein the first and second mixing modules comprise transistors which are complementary to each other.

Abstract: A device for receiving a RF signal (1; 21) with loop-through output (16) is provided. The device comprises: an input (3) receiving a RF input signal (2); an analog-digital converter (8) converting the RF input signal (2) to a digital signal (9); a digital signal processing unit (10) digitally processing the digital signal (9); a digital-analog converter (14) converting the processed digital signal (13) to a loop-through RF signal (15) corresponding to the RF input signal (2); and a loop-through output (16) outputting the loop-through RF signal (15).

Abstract: The present invention relates to an all n-type transistor current mirror for mirroring an input current to an output current. The current mirror comprises an input n-type transistor (T4, QO, T1) interposed between a positive supply plane (VCC) and an input node (104, 202, 310) with its collector being connected to the positive supply plane (VCC) and its emitter being connected to the input node (104, 202, 310). An output n-type transistor (T3, Q1, T2) is interposed between the positive supply plane (VCC) and an output node (106, 204, 314) with its collector being connected to the positive supply plane (VCC) and its emitter being connected to the output node (106, 204, 314). A feedback circuit equals base-emitter voltages of the input (T4, QO, T1) and the output transistor (T3, Q1, T2) in order to mirror the emitter current of the input transistor (T4, QO, T1) to the emitter current of the output transistor (T3, Q1, T2).

Abstract: In a method of tuning a receiver for a digital signal (MPEG2-TS), an input signal (RF-in) is filtered (In-filt, Band-filt) to obtain a processed signal, a digital figure of merit (BER) is determined (Mix/Osc/IF amp IF-downconv-2, C) from the processed signal, and the filtering step (In-filt, Band-filt) is fine-adjusted (?P, PLL, DAC1-DAC3) in dependence on the digital figure of merit (BER).

Abstract: An integrated variable capacitance with low losses comprises an array (1) of switched capacitors (2-8). When using an array (1) of switched capacitors (2-8) to form a quasi continuously variable capacitor, a continuity of capacitance as function of the digital control signal to the array (1) leads to overall behavior of the series resistance of the array (1) as function of the capacitance that for some applications may be undesirable. Therefore a topology for a switched array (1) is proposed that allows to set series resistance relatively independent from capacitance. The array (1) may be fully or partially integrated in tunable LC filters, also in TV tuners.

Abstract: Optical disk systems comprising photo detectors (1) for detecting optical disks comprising amplifiers and slicers (2-5) and delay-difference detectors (6) for detecting delay differences in sliced amplified detection signals are improved by installing delaylineless delay-difference detectors (6) comprising combinatorial-logic circuits (7,8) like inverters, ORs, NORs, ANDs, NANDs and sequential-logic circuits (11-18) like SetResetFlipFlops. Without the prior art delay lines, said delay-difference detectors (6) are of a lower complexity and low costly and can be well integrated. By introducing a first pair of sequential-logic circuits (11,12,15,16) for detecting delay differences between rising edges and a second pair of sequential-logic circuits (13,14,17,18) for detecting delay differences between falling edges, both kinds of edges are being used and the influence of time-jitter is less compared to the situation where just one kind of edge is used.

Abstract: The present invention relates to Current mirror for generating a constant mirror ratio, comprising an output transistor (Tout) having a base, an emitter and a collector, wherein a current flowing through the collector of said output transistor (Tout) constitutes an output current (Iout) of said current mirror and the collector of said output transistor (Tout) is connectable to an output circuit, a buffer transistor having a base, an emitter and a collector, wherein the emitter of the buffer transistor is connected to the base of the output transistor, a buffer current source for providing a fixed buffer current, wherein said buffer current source is connected to the collector of the buffer transistor, and a buffer base voltage control means having an input connected to the base of the output transistor and an output connected to the base of the buffer transistor, wherein the base voltage control means is adapted to controlling a voltage at the base of the buffer transistor in response to a current at the inpu

Abstract: An optical disk system includes at least one photo detector connected with a variable gain amplifier, a slicer, and a generator which is in the feedback path between the slicer and amplifier. A differential time delay detector provides the output of the optical disk system. The generator is configured for controlling the amplifier non-linearly so that time constants of the control loop of the amplifier which depend upon the level of the input signals are compensated and the timing behavior of the control loop of the amplifier has a more continuous character. A capacitor forms part of an integrator for making the mean value of the output voltage signal of the slicer equal to zero.

Abstract: The present invention relates to a method of controlling a variable gain amplifier having at least one semiconductor switch, the amplifier having a first gain when the semiconductor switch is in a first steady state and a first gate voltage is applied to the semiconductor switch, and the amplifier having a second gain when the semiconductor switch is in a second steady state and a second gate voltage is applied to the semiconductor switch, whereby a sequence of third gate voltages is applied to the semiconductor switch to transition between the first and second gains.

Abstract: An LC oscillator (I) comprises a cross-coupled PMOS transistor pair (Ma, Mb) coupled to a pair of capacitors (Cva, Cvb) and a pair of inductances (La, Lb). To enhance the signal amplification of the oscillator, a pair of auxiliary transistor circuits (Qa, Qb; Na, Nb) is provided which are coupled between the drain and, preferably, the source of each PMOS transistor. The capacitors (Cva, Cvb) are preferably variable capacitors and the inductances (La, Lb) are preferably connected to ground to allow a enlarged tuning voltage range.

Abstract: An electronic circuit is provided which can autonomously handle an input current (Ii) having a relatively wide dynamic range without being overdriven. The electronic circuit comprises an amplifier stage (AMPST) having an input (IP) for receiving the input current (Ii) and an output (OP) for supplying an output current (Io), such that, during operation, the strength of the output current (Io) increases in response to an increasing strength of the input current (Ii) as long as the strength of the input current (Ii) has not exceeded an input reference level. The strength of the output current (Io) is kept approximately constant when the strength of the input current (Ii) has exceeded the input reference level but has not exceeded a further input reference level. The strength of the output current (Io) decreases in response to an increasing strength of the input current (Ii) when the strength of the input current (Ii) has exceeded the further input reference level.

Abstract: An improved differential inverter comprising a differential inverter having a differential input for receiving a first input signal and a second input signal, said inverter further comprising a differential control input for receiving a first control signal and a second control signal. The improved differential inverter further comprises a differential output for transmitting a first output signal and a second output signal. The improved differential inverter further comprises a controlled bias generator that generates the second vector of input signals in response to a bias control signal. The control bias signal is generated at an output of a voltage divider coupled to the differential output of the differential inverter said bias control signal being indicative for a DC voltage of the of the differential output.

Abstract: A PLL circuit with a series coupling of a charge pump, a loop filter and a voltage-controlled oscillator generating an output frequency (f), the voltage-controlled oscillator including tunable devices controlled by a first control signal generated by the loop filter, the PLL circuit includes a leakage compensation circuit for generating a leakage compensation signal to modify a control of the voltage-controlled oscillator, the leakage compensation signal being indicative for a leakage current in the tunable devices of the voltage-controlled oscillator.

Abstract: A low dropout voltage regulator comprising a series-regulating element (T1) between an input (I) and an output (O) of the voltage regulator, and a differential input error amplifier (1) having a first output (O1) coupled to a control input of the series-regulating element (T1), characterized in that the error amplifier (1) further comprises a second output (O2) coupled to the output (O) via a high-pass filter (5, C1, R1).