Abstract: In a digital transmission system including a transmitter (2) coupled via a channel (4) to a receiver (6) a detection signal r.sub.k is compared with a number of reference values to determine the destination symbols a.sub.k. Since the size of the received signal r.sub.k is not known in advance, the ratio between the detection signal and the reference values is to be determined by an adapting circuit (16) on the basis of the received signal and the decisions made. The problem may then occur that as a result of an initially erroneous value of the ratio between detection signal and reference values not a correct adaptation is made. By recognizing such a situation because specific values of the symbols a.sub.k are lacking, in such a situation said ratio can be brought to such a value by the correction circuit (18) that all the values of a.sub.k again occur.

Abstract: A differential amplifier comprises a Darlington differential pair (T.sub.1 /T.sub.3, T.sub.2 /T.sub.4) and a cross-coupled transistor pair (T.sub.5, T.sub.6) to increase the transconductance of the Darlington differential pair (T.sub.1 /T.sub.3, T.sub.2 /T.sub.4). The negative input impedance of the differential amplifier as a result of the presence of the cross-coupled differential pair (T.sub.5, T.sub.6) is compensated for at high frequencies and the gain of the differential amplifier is reduced by a compensation circuit with a capacitor (30) between the control electrodes of the transistors of the cross-coupled differential pair (T.sub.5, T.sub.6) and with resistors (26, 28) in series with the control electrodes of the transistors of the cross-coupled differential pair (T.sub.5, T.sub.6).

Abstract: An electronic arrangement for generating a modulated carrier signal in a transmitter includes a sigma-delta (one-bit) signal converter and a mixer. The sigma-delta converter includes, in a closed signal loop, an adder, a low pass filter, and a pulse shaper driven with a specific sample rate. The mixer is driven with a carrier frequency fc and has an input coupled with an output of the pulse shaper. The carrier frequency fc is equal to or an integer multiple of the half sample rate.

Abstract: A continuous-time analog signal filter arrangement, for realizing a magnitude frequency characteristic which increases for increasing frequencies over a part of the operating frequency range of the filter arrangement, includes an input terminal (1) for receiving an input signal, an output terminal (9) for supplying an output signal which is a filtered version of the input signal, and a number of N integrator elements (5.1, 5.2, . . . , 5.N) connected in series and being included in a feedback loop, where N.gtoreq.2. For each of the N integrator elements the relation holds that the input signal of an integrator element is a differentiated version of its output.

Abstract: Electronic receive arrangement for receiving a modulated carrier signal, which arrangement comprises a mixer/demodulator driven with the carrier frequency fc, at least one adder included in a closed signal loop, a low-pass filter, and a pulse shaper constituted by a sigma-delta (one-bit) signal converter and driven with the sampling frequency fs and also comprises a digital decimation filter. The signal loop includes the mixer/demodulator so that the modulated carrier signal is applied to the adder and the output signal of the adder is applied to the mixer/demodulator. The signal loop also comprises a second mixer driven with frequency fc, and the frequencies fs and fc present a common multiple.

Abstract: Analog-to-digital converter comprising a plurality of sigma-delta modulators, the input of the pulse shaper of a modulator always being coupled to the input of a next modulator via a coupling filter, and the output of the modulators being connected to the summing circuit via decimators, whereas in the decimators the filter function of the coupling filters is compensated. The loop filters in the modulators are described by third-order transfer functions with real poles and zeros.

Abstract: A balanced filter circuit includes only one balanced amplifier (10) having an inverting input (6) and a non-inverting input (5) and an inverting output (7) and a non-inverting output (8) for realization of filter transfer functions Uout/Uin of the second or higher order from an input signal Uin at input terminals (1, 2) to an output signal Uout at output terminals (3, 4) having passive admittances which are composed of a parallel-combination of a resistor (R42, R44) and/or a capacitor (C41, C44) and/or a number of series-combinations of a resistor (R41, R43, R45) and a capacitor (C42, C43, C45).

Abstract: Latch circuit including a differential amplifier T1, T2 for amplifying a data signal D, ND to be latched, applied to the inputs 1, 2 of the differential amplifier, a flip-flop T3, T7, T4, T8 for latching the amplified data signal across the load impedances 6, 7 which are connected to the transistors T1, T2 through switching transistors T5 and T6 if the clock signal CLK is high and are disconnected therefrom if the clock signal is low. When there is a high clock signal the emitter junctions 11, 14 of the flip-flop are currentless. The transistors T5 and T6 fix the voltage at these junctions, and thereby avoid a variation of the junction voltage. Consequently, the decision accuracy of the latching operation is retained even with high clock signal frequencies.

Abstract: 1-Bit signma-delta modulator having a loop filter (5,6,8), a first negative feedback loop (13,7,8) and a second negative feedback loop (14,4,5,6,8). The filter sections 5 and 8 are passive filter elements and filter section 6 is a high-gain active filter element. A circuit of this type makes a very high clock rate possible in the decision switch 10.

Abstract: A balanced filter circuit has a number of balanced pushpull amplifiers (10) whose inputs (11, 12) and outputs (13, 14) are coupled to filter resistors (20, 21, 22, 25, 27A/B) and filter capacitors (23, 24, 26A/B). In order to adjust the filter, the currents from the filter resistors to the inputs of the balanced amplifiers are varied by means of adjustable balanced multipliers (40).

Abstract: A combined current difference and operational amplifier circuit (10) for use either as or in a filter embodied in an integrated receiver includes inputs (I.sub.A and I.sub.B) for oppositely phased current signals which are applied to a current mirror circuit formed by first and second NPN transistors (Q1,Q2) having their bases connected to a junction (20). Equal value resistors (R1,R2) are serially connected in the emitter circuits of the first and second transistors, respectively and the current inputs are coupled to the free ends of the resistors. The base-collector path of a third NPN transistor (Q3) is connected between the free end of one of the resistors (R1) and the junction (20). A current difference signal (i.sub.b -i.sub.a) derived from the free end of the other one of the resistors is applied to the virtual ground input of an operational amplifier formed by a common emitter stage (Q4) coupled to an emitter follower (Q5).

Abstract: The invention relates to an active RC filter arrangement comprising a balanced amplifier (A.sub.1) which can be extended to obtain an n.sup.th -order filter arrangement. Once a general n.sup.th -order filter arrangement has been created it can be modified to obtain, inter alia, a low-pass, a high-pass or an all-pass n.sup.th -order active RC filter by merely changing the values of the resistors and capacitors.

Abstract: A third-order all-pass network for a delay circuit is formed by four coupled transconductors (G.sub.10 to G.sub.13) which are each represented by two transistors whose bases constitute the inputs and whose collectors constitute the outputs of the transconductor. A first input of these transconductors (G.sub.10 to G.sub.13) is connected to ground (3). Between the second inputs (25,26) of the first transconductor (G.sub.10) and the second transconductor (G.sub.11) a first capacitor (C.sub.1) is arranged, between the second inputs (26,27) of the second transconductor (G.sub.11) and the third transconductor (G.sub.12) a second capacitor (C2) is arranged, and between the second inputs (27,28) of the third transconductor (G.sub.12) and the fourth transconductor (G.sub.13) and a third capacitor (C3) is arranged. Further, a fourth capacitor (C4) is arranged between the second inputs (25,27) of the first transconductor (G.sub.10) and the third transconductor (G.sub.

Abstract: Asymmetric polyphase filer having first to fourth input terminals for applying thereto a 4-phase input signal including first to fourth signal vectors, respectively, which succeed one another in phase each time through 90.degree., first to fourth intercoupled identical filter sections, respectively, connected to the terminals, at least one of the odd and even filter sections being coupled to two output terminals, said filter sections having constant reactances.

Abstract: A third-order all-pass network for a delay circuit is formed by four coupled transconductors (G.sub.10 to G.sub.13) which are each represented by two transistors whose bases constitute the inputs and whose collectors constitute the outputs of the transconductor. A first input of these transconductors (G.sub.10 to G.sub.13) is connected to ground (3). Between the second inputs (25,26) of the first transconductor (G.sub.10) and the second transconductor (G.sub.11) a first capacitor (C.sub.1) is arranged, while between the second imputs (26,27) of the second transconductor (G.sub.11) and the third transconductor (G.sub.12) a second capacitor (C2) is arranged, and between the second inputs (27,28) of the third transconductor (G.sub.12) and the fourth transconductor (G.sub.13) a third capacitor (C3) is arranged. Further, a fourth capacitor (C4) is arranged between the second inputs (25,27) of the first transconductor (G.sub.10) and the third transconductor (G.sub.

Abstract: The invention relates to an active symmetrical balance hybrid circuit. The hybrid circuit includes an input, an output and an in/output as well an impedance circuit per half section connected to the input and output which is connected between the in/output and one or more virtual ground points. Between a virtual ground point and one of the supply lines a signal transistor is inserted. The hybrid circuit further includes per half section two auxiliary transistors connected between the supply lines and the in/output. The auxiliary transistors multiply by the same factor the current flowing through a signal transistor together with which the auxiliary transistor is incorporated in a current mirror circuit. A signal transistor can be incorporated in a current mirror circuit with one or two auxiliary transistors in the same half section, but also by means of a universal coupling of the two half sections both with an auxiliary transistor in the one and an auxiliary transistor in the other half section.

Abstract: In a filter arrangement, a first junction capacitor is arranged between the inverting output and the non-inverting input of a fully balanced amplifier and a second junction capacitor is arranged between the non-inverting output and the inverting input. Additionally, a first resistor is arranged between a first input terminal and the non-inverting input and a second resistor is arranged between a second input terminal and the inverting input. A first current source is connected to the non-inverting input and a second current source is connected to the inverting input. The current sources produce the reverse voltages for the junction capacitors across the resistors to define the capacitance values of these capacitors.

Abstract: In a filter arrangement having a transconductance circuit, a first capacitor is arranged between the inverting output and the non-inverting input of a balanced amplifier and a second capacitor is arranged between the non-inverting output and the inverting input. The outputs of a transconductance circuit (transconductor) are connected to the non-inverting input and the inverting input, which transconductor converts a balanced input voltage applied to the inputs into a balanced output current, its transconductance being variable by means of a variable current source. Further, the transconductor is loaded by a load circuit comprising a first current-source transistor and a second current-source transistor whose common base is connected, via a diode, to the junction point between two resistors arranged between the outputs of the transconductor.

Abstract: In an adaptive filter a plurality of outputs (5, 7, 9, 11) of a delay circuit (3) are coupled via coefficient control circuits (21, 23, 25, 27) to a plurality of inputs (91, 93, 95, 97) of an adder circuit (89). The control signal inputs (29, 31, 33, 35) of the coefficient control circuits each receive a control signal via first integrators (37, 39, 41, 43) from first multiplier circuits (53, 55, 57, 59). A further output (85) of the delay circuit (3) controls a further input (87) of the adder circuit (89). The output signal from the adder circuit is controlled by a control circuit (121) which receives a control signal from a second multiplier circuit (103) via a second integrator (109) and a circuit having an exponential transfer function (113).

Abstract: A transconductance amplifier comprising a voltage divider including two identical resistors (R.sub.o) connected between the bases (3, 4) of two first transistors (T.sub.o1, T.sub.o2) arranged as a differential pair, each having a first emitter area (e.sub.o). The junction point of said resistors (R.sub.o) is connected to the base of a second transistor (T.sub.1) having a second emitter area (2e.sub.1), whose emitter, like that of the first transistors (T.sub.o1, T.sub.o2), is connected to a current source (6). For a ratio between the second and the first emitter areas (2e.sub.1 ; e.sub.o) equal to 4:1 the difference between the output currents (I.sub.1, I.sub.3) of the first transistors (T.sub.o1, T.sub.o2) increases as a linear function of the input voltage over a range which is as large as possible.