Patents by Inventor Johannes Wang

Johannes Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190296541
    Abstract: A mobile application includes a motive power circuit having a power storage device and an electrical load, where the power storage device and the electrical load are selectively electrically coupled through a power bus. The application includes a power distribution unit (PDU) electrically interposed between the power storage device and the electrical load, where the PDU includes a breaker/relay positioned on one of a high side and a low side of the power storage device. The breaker/relay includes a fixed contact and a moveable contact selectively electrically coupled to the fixed contact, where the moveable contact allows power flow through the power bus when electrically coupled to the fixed contact, and prevents power flow through the power bus when not electrically coupled to the fixed contact. The breaker/relay includes an armature coupled to the moveable contact, and capable to open or close the motive power circuit.
    Type: Application
    Filed: April 10, 2019
    Publication date: September 26, 2019
    Inventors: Martin Wayne Mensch, Brandon William Fisher, Robert Stephen Douglass, Austin Robert Zurface, Jeff Howard Urian, James David, Bharath Suda, Asheesh Soni, Karsten Gerving, Guido Völlmar, Gerd Schmitz, Christoph Bausch, Ute Molitor, Lutz Friedrichsen, Kai Schroeder, Julia Otte, Madeline Philipsohn, Norbert Roesner, Volker Lang, Johannes Meissner, Paolo D'amico, Jalpa Shah, Meng Wang, Damrongrit Piyabongkarn, Niles Stephen Ramseyer, Dennis Dukaric, Matt Haylock
  • Patent number: 10417612
    Abstract: Systems, methods, and software are disclosed herein for implementing enhanced search environments. In one implementation, an enhanced service environment includes a working set service that receives event signals initiated by working set agents in various application services. The working set agents communicate the event signals to nominate events occurring in the application services for inclusion in a working set of information specific to a user. The nominations may be based at least in part on a working set model specific to the user. In response to receiving the event signals, the working set service determines which of the events qualify for inclusion in the working set of information based at least in part on the working set model. For each event that qualifies for inclusion, the working set is modified to include at least the event.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 17, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Johannes Ernst Gehrke, Eirik Knutsen, Øystein Torbjørnsen, James Charles Kleewein, Bård Kvalheim, Øivind Wang
  • Patent number: 10360697
    Abstract: A method for performing Computed Tomography (CT) reconstruction includes acquiring a sparse measurement matrix using a CT scanner and applying a reconstruction process over a number of iterations to reconstruct image data from the sparse measurement matrix. The reconstruction process performed during each respective iteration includes generating a random view subset and determining a portion of the sparse measurement matrix corresponding to the random view subset. The reconstruction process further includes performing a stochastic gradient descent on the portion of the sparse measurement matrix to yield an image, applying a proximal total variation regularization to the image, and adjusting a step size associated with the stochastic gradient descent.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: July 23, 2019
    Assignee: Siemens Healthcare GmbH
    Inventors: Boris Mailhe, Johannes Flake, Qiu Wang, Mariappan S. Nadar
  • Patent number: 10321851
    Abstract: The invention is directed to a system and method for providing an ARDS indication of a patient comprising a sampling device for obtaining a gas sample of the exhaled breath of a patient, a measuring unit for measuring a content of n-octane in the exhaled breath of a patient, a controller which is able to distinguish if the patient has or may develop ARDS based on the content of n-octane in the exhaled breath of a patient resulting in a ARDS indication of the patient and provided with a protocol for providing output regarding the ARDS indication of the patient, and a user interface for indicating the ARDS indication to a user.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: June 18, 2019
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Johannes Weda, Teunis Johannes Vink, Yuanyue Wang, Lieuwe Durk Jacobus Bos, Tamara Mathea Elisabeth Nujsen
  • Publication number: 20190175122
    Abstract: A method for determining a deformation measurement of a couch in a medical procedure may include determining a first deformation measurement of the couch at a reference point, the first deformation measurement corresponding to a first working position of the couch. The method may also include determining a second deformation measurement of the couch at the reference point, the second deformation measurement corresponding to a second working position of the couch. The method may further include determining a difference between the first deformation measurement and the second deformation measurement and causing an adjustment of one of the first working position and the second working position of the couch based on the difference between the first deformation measurement and the second deformation measurement.
    Type: Application
    Filed: November 28, 2018
    Publication date: June 13, 2019
    Applicant: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventors: Johannes STAHL, Supratik BOSE, Li WANG
  • Publication number: 20190175942
    Abstract: A method may include acquiring a first image including a target point and a first reference point, the target point corresponding to at least one part of a subject, the first reference point corresponding to a first marker disposed on the couch of the medical device; determining a first spatial position of the first marker, the first spatial position corresponding to a first working position of the couch; determining a first spatial position of the at least one part of the subject based on the first image and the first spatial position of the first marker; determining a second spatial position of the first marker, the second spatial position corresponding to a second working position of the couch; determining a second spatial position of the at least one part of the subject based on the second spatial position of the first marker and the first spatial position of the at least one part of the subject.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 13, 2019
    Applicant: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventors: Johannes N STAHL, Supratik BOSE, Li WANG
  • Patent number: 10309129
    Abstract: The invention relates to a motor vehicle door lock with a locking mechanism comprising a rotary latch and a pawl, a trigger lever which acts on the pawl, a blocking lever which acts on the trigger lever, a first actuating lever which acts on the trigger lever and which acts on the blocking lever via a first leg spring, and a second actuating lever which acts on the trigger lever and which acts on the blocking lever via a second leg spring.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: June 4, 2019
    Assignee: Kiekert Aktiengesellschaft
    Inventors: Elena Suholutskaja, Johannes Theodor Menke, Xinlei Wang
  • Patent number: 8019975
    Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: September 13, 2011
    Assignee: Seiko-Epson Corporation
    Inventors: Cheryl Senter Brashears, Johannes Wang, Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
  • Patent number: 7958337
    Abstract: An apparatus and method for executing instructions having a program order. The apparatus comprising a temporary buffer, tag assignment logic, a plurality of functional units, a plurality of data paths, a register array, a retirement control block, and a superscalar instruction retirement unit. The temporary buffer includes a plurality of temporary buffer locations to store result data for executed instructions, wherein the temporary buffer locations are arranged in a plurality of groups of temporary buffer locations. The tag assignment logic is configured to concurrently assign a tag to each instruction in a first set of instructions, wherein the tags are assigned such that the respective tag assigned to each of the instructions in the first set of instructions identifies a different one of the temporary buffer locations in a first one of the groups of temporary buffer locations.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: June 7, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Johannes Wang, Sanjiv Garg, Trevor Deosaran
  • Patent number: 7941635
    Abstract: The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: May 10, 2011
    Assignee: Seiko-Epson Corporation
    Inventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
  • Patent number: 7934078
    Abstract: An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: April 26, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Johannes Wang, Sanjiv Garg, Trevor Deosaran
  • Patent number: 7861069
    Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: December 28, 2010
    Assignee: Seiko-Epson Corporation
    Inventors: Cheryl D. Senter, Johannes Wang
  • Patent number: 7844797
    Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: November 30, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Cheryl D. Senter, Johannes Wang
  • Patent number: 7802074
    Abstract: A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: September 21, 2010
    Inventors: Sanjiv Garg, Kevin Ray Iadonato, Le Trong Nguyen, Johannes Wang
  • Patent number: 7739482
    Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: June 15, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
  • Patent number: 7721070
    Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: May 18, 2010
    Inventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
  • Patent number: 7664935
    Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: February 16, 2010
    Inventors: Brett Coon, Yoshiyuki Miyayama, Le Trong Nguyen, Johannes Wang
  • Publication number: 20090217001
    Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.
    Type: Application
    Filed: May 6, 2009
    Publication date: August 27, 2009
    Inventors: Cheryl D. Senter, Johannes Wang
  • Patent number: 7555632
    Abstract: The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: June 30, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
  • Publication number: 20090158014
    Abstract: An apparatus and method for executing instructions having a program order. The apparatus comprising a temporary buffer, tag assignment logic, a plurality of functional units, a plurality of data paths, a register array, a retirement control block, and a superscalar instruction retirement unit. The temporary buffer includes a plurality of temporary buffer locations to store result data for executed instructions, wherein the temporary buffer locations are arranged in a plurality of groups of temporary buffer locations. The tag assignment logic is configured to concurrently assign a tag to each instruction in a first set of instructions, wherein the tags are assigned such that the respective tag assigned to each of the instructions in the first set of instructions identifies a different one of the temporary buffer locations in a first one of the groups of temporary buffer locations.
    Type: Application
    Filed: February 26, 2009
    Publication date: June 18, 2009
    Applicant: Seiko Epson Corporation
    Inventors: Johannes Wang, Sanjiv Garg, Trevor Deosaran