Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution for enhanced resource utilization and performance throughput. The computer system architecture includes an instruction fetch unit for fetching program instruction sets. Each instruction set includes a plurality of fixed length instructions with a prescribed program order (in-order). The architecture also includes an instruction execution unit for dynamically examining the instruction sets and scheduling instructions for execution, including out-of-order execution, among a plurality of functional units. The data results of the executed instructions are concurrently distributed to a temporary buffer and a register file array and managed by associated control logic, including a register renaming unit, a dependency checker unit, done control unit, and retirement control unit.

Abstract: A VLSIC page printer controller includes an instruction processor which responds to a host computer and a printer video processor for accessing data from memory under the control of the instruction processor and serializing data for transfer to a printer through a video port. An I/0 interface interconnects the printer controller with an I/O bus to which is connected a host computer, memory devices, and other peripheral devices. An internal memory interface connects the printer controller to memory, and the printer video processor is provided with direct memory access (DMA). Data and instruction caches and an instruction ROM are provided on-chip. A RISC instruction processing unit includes as an integral part thereof the special function circuits of orthogonal rotator, bit/byte mirror, and pixel modification.

Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instruction sets and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers which are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

Abstract: A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one of more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

Abstract: Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler can be located completely inside the table entry, or it can transfer control to additional handler code.

Abstract: A method for use in a microprocessor to return execution to a main program after processing an interruption to the sequential processing of instructions from the main instruction stream is disclosed. The method comprises fetching instructions from a main instruction stream to a main buffer section of a prefetch buffer and executing said fetched instructions. The method also provides for handling interruptions to the processing of the main instruction stream and allowing return to the main instruction stream without requiring prefetching of instructions already fetched. Similarly, the method provides for handling interruptions of the processing of interruptions of the processing of the main instruction stream.

Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions.

Abstract: A VLSIC page printer controller includes an instruction processor which responds to a host computer and a printer video processor for accessing data from memory under the control of the instruction processor and serializing data for transfer to a printer through a video port. An I/O interface interconnects the printer controller with an I/O bus to which is connected a host computer, memory devices, and other peripheral devices. An internal memory interface connects the printer controller to memory, and the printer video processor is provided with direct memory access (DMA). Data and instruction caches and an instruction ROM are provided on-chip. A RISC instruction processing unit includes as an integral part thereof the special function circuits of orthogonal rotator, bit/byte mirror, and pixel modification.