Abstract: A method and apparatus for providing programmable active termination of transmission lines with substantially reduced DC power consumption.

Abstract: The present invention provides for x-ray imaging and ultrasound imaging of a body region of interest in a spatially correlatable manner. The resultant x-ray and ultrasound images may be combinatively employed to provide three-dimensional information regarding a location of interest within the body, and is particularly apt for use in the analysis/biopsy of potential lesions and suspicious masses in a female breast. The invention provides for direct body contact by an ultrasound imaging head, as well as targeted ultrasound imaging of a selected portion of the region from which x-ray images are obtained. A user interface system facilitates various procedures including ultrasound guided needle biopsy procedures.

Abstract: True and complement data signals are provided to a multiplexer, which selects one of them based on a selection signal for capture by a single scannable latch in response to a clock signal. The scannable latch then provides the captured signal for testing by testing logic.

Abstract: A row-select circuit for an organic light emitting diode display propagates a gating pulse through a shift register. This gating pulse is synchronized with a system clock signal and is used to selectively apply a plurality of broadcast control signals to a selected row of pixels on the display. The line scanning circuitry is controlled to clear and autozero the pixels in the display either one line at a time or the entire image frame at a time. According to another aspect of the invention, the clearing of a row of pixels in the display is performed over several line intervals before the row is autozeroed and loaded with new values. According to yet another aspect of the invention, the broadcast control signals may be adapted to achieve the best performance for each display device.

Abstract: A method and apparatus for providing programmable active termination of transmission lines with substantially reduced DC power consumption.

Abstract: An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit.

Abstract: An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit.

Abstract: An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit.

Abstract: An impedance matching system and a network for automatic impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises a control circuit which varies a control voltage proportionally to the frequency of voltage transients that occur on the driver circuit output, an adjustment mechanism which provides a linear motion proportional to the control voltage, and an adjustable length transmission line whose length is adjusted in proportion to the frequency of voltage transients on the driver circuit output and whose impedance, which is purely reactive, is proportional to its length. The purpose of the adjustable length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver network to the driver circuit. In the preferred embodiment, the impedance matching network is manufactured on the same chip as the driver circuit.

Abstract: A burner construction having a body portion fabricated from a base material and coating material covering the base material. The base material is formed of copper or copper alloy having a conductivity of no less than about 100 watts/meter/.degree. C. Alternatively the base material can be silver. The coating material comprises nickel or nickel based alloy which can be an autocatalytic plating.

Abstract: A CMOS off-chip driver circuit and a method of operating the circuit are provided. The circuit has two pull-down transistors and two pull-up transistors, each pull-up transistor has a gate. A voltage source provides voltage at a logic-high output voltage of approximately 3.3 volts. An output terminal is provided. Initially, a logic-low output voltage is applied to the gate of each of the two pull-up transistors. A condition is detected in which the voltage of the output terminal is greater than a predetermined threshold voltage. The predetermined threshold voltage is between approximately 2.5 volts and approximately 3.3 volts. The voltage applied to the gate of each of the pull-up transistors is raised to an intermediate level that is greater than the logic-low output voltage and less than the logic-high output voltage while the condition is detected. The intermediate level may be approximately 1.5 volts.

Abstract: An off-chip receiver circuit for interfacing an integrated circuit of a 2.5 Volt CMOS technology to a 3.3 Volt LVTTL bus. The off-chip receiver includes protection circuitry for preventing overstressing of the gate oxide caused by undershoot/overshoot peaks of -1 volt to 6 volts on the input.

Abstract: A memory Array Built-In Self-Test (ABIST) circuit is disclosed that will test a multi-port memory array. A programmable pattern generator for the ABIST circuit allows for different R/W data operations to be performed at the same or adjacent address locations within a multi-port memory array. The programmable pattern generator comprises a data generator, a read/write controller, and an address counter, each having the same number of outputs as ports of the multi-port memory array. The programmable pattern generator also comprises a frequency controller. The data generator is programmed with the appropriate data patterns for the memory array, and the read/write controller is programmed with the appropriate read/write patterns for the memory array. The address counter is to provide the same or different addresses on each port of the multi-port array, and the frequency controller is programmed with the appropriate frequency information to determine the number of read/write operations per cell in the memory array.

Abstract: A topology for arranging a plurality of transistors between a signal source and an off-chip receiver, using a single power supply voltage. A pass through NFET has a gate controlled by a network comprised of two transistors arrayed between the power supply voltage and the drain of the NFET, which limits overshoots to the power supply voltage and reduces undershoots. Further reduction of undershoots is accomplished by an additional network of transistors, optimally including a PFET in series with the pass through NFET.

Abstract: An ABIST circuit for testing a memory array has a blanket write subcycle (WC), an RC3 subcycle, and an RC4 subcycle. The ABIST circuit includes a programmable pattern generator that provides eight programmable data bits, eight programmable read/write bits, and two programmable address frequency bits to determine the specific test patterns applied to the memory array. The address frequency bits determine how many memory cycles will be performed on each cell of the memory array. In X1 mode, only one memory cycle is performed on each cell during any given subcycle. In X2 mode, two memory cycles are performed on each cell, allowing a cell to be written, then subsequently read in the same subcycle. In X4 mode, four memory cycles are performed on each cell, and in X8 mode, all eight bits of read/write and data are used on each cell, resulting in eight memory cycles for each cell within the memory array.

Abstract: The present invention provides a device for testing memory having write cycles and read cycles. A BIST state machine changes the data applied to the memory's DI port during read cycles to a value different from that of the data stored in the currently addressed memory location. The BIST-generated expect data also is at a different value from that of data at the memory's DI port and at the same value as the data stored at the current memory address location during read operations. With this arrangement, flush through defects can be detected which would not have been detectable by prior BIST machines.

Abstract: An ABIST circuit for testing a memory array has a blanket write subcycle (WC), an RC.sub.3 subcycle, and an RC.sub.4 subcycle. The ABIST circuit includes a programmable pattern generator that provides eight programmable data bits, eight programmable read/write bits, and two programmable address frequency bits to determine the specific test patterns applied to the memory array. The address frequency bits determine how many memory cycles will be performed on each cell of the memory array. In X1 mode, only one memory cycle is performed on each cell during any given subcycle. In X2 mode, two memory cycles are performed on each cell, allowing a cell to be written, then subsequently read in the same subcycle, In X4 mode, four memory cycles are performed on each cell, and in Xg mode, all eight bits of read/write and data are used on each cell, resulting in eight memory cycles for each cell within the memory array.

Abstract: A method and circuit are provided to detect if any bit stored in a given location in a memory is different from the data expected. The circuit includes logic to read each of the bits stored in the cells at given locations from memory and to generate a fail signal based on the data expected to be stored if the stored data is different from the expected data. The circuit also preferably includes logic to compare the True data and expect data read from each cell and generating the fail signal if they are the same. Additional logic circuitry is also preferably provided which determines if a node of the circuit remains in a precharged condition.

Abstract: A test method and structure is provided to determine the end count of a predetermined succession or series of binary numbers wherein one number and its relation in the succession to the end count number is known. The structure includes a circuit for generating a binary digit output and a device for storing at least a portion of the said one number which preferably is the penultimate number in a sequential series. A succession of binary numbers is generated as output of the circuit. the outputted numbers are compared to the portion of the stored number. A READY signal is outputted when the stored number compares with the outputted number. On a subsequent cycle, a control signal is generated when the generated number following the READY signal corresponds to the end count number. The inventor also contemplates programmable end count numbers.

Abstract: An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory.