Patents by Inventor John A. Iacoponi

John A. Iacoponi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10050118
    Abstract: In one aspect a semiconductor device as set forth herein can include a spacer having a first section of a first material and a second section of a second material, the second section disposed above a certain elevation and the first section disposed below the certain elevation. In one aspect a semiconductor device as set forth herein can include a conductive gate structure having a first length at elevations below a certain elevation and a second length at elevations above the certain elevation, the second length being less than the first length. A semiconductor device having one or more of a plural material spacer or a reduced length upper elevation conductive gate structure can feature a reduced likelihood of electrical shorting.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Ryan Ryoung-han Kim, Chanro Park, William James Taylor, Jr., John A. Iacoponi
  • Publication number: 20150318345
    Abstract: In one aspect a semiconductor device as set forth herein can include a spacer having a first section of a first material and a second section of a second material, the second section disposed above a certain elevation and the first section disposed below the certain elevation. In one aspect a semiconductor device as set forth herein can include a conductive gate structure having a first length at elevations below a certain elevation and a second length at elevations above the certain elevation, the second length being less than the first length. A semiconductor device having one or more of a plural material spacer or a reduced length upper elevation conductive gate structure can feature a reduced likelihood of electrical shorting.
    Type: Application
    Filed: May 5, 2014
    Publication date: November 5, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong XIE, Ryan Ryoung-han KIM, Chanro Park, William James Taylor, JR., John A. IACOPONI
  • Patent number: 8946075
    Abstract: One method includes performing a first etching process to form a contact opening in a layer of insulating material that exposes a portion of a gate structure of the transistor, performing a second etching process on the exposed portion of the gate structure to thereby define a gate recess, selectively forming an oxidizable material in the gate recess, converting the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to a source/drain region. A device includes an oxide material that is positioned at least partially in a recess formed in a gate structure, wherein the oxide material contacts a conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: February 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiuyu Cai, Ruilong Xie, John A. Iacoponi
  • Patent number: 8940633
    Abstract: One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable material on the exposed gate structure, converting at least a portion of the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to the source/drain region. A novel transistor device disclosed herein includes an oxide material positioned between a conductive contact and a gate structure of the transistor, wherein the oxide material contacts the conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiuyu Cai, Ruilong Xie, John A. Iacoponi
  • Publication number: 20140252424
    Abstract: One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable material on the exposed gate structure, converting at least a portion of the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to the source/drain region. A novel transistor device disclosed herein includes an oxide material positioned between a conductive contact and a gate structure of the transistor, wherein the oxide material contacts the conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Xiuyu Cai, Ruilong Xie, John A. Iacoponi
  • Publication number: 20140252425
    Abstract: One method includes performing a first etching process to form a contact opening in a layer of insulating material that exposes a portion of a gate structure of the transistor, performing a second etching process on the exposed portion of the gate structure to thereby define a gate recess, selectively forming an oxidizable material in the gate recess, converting the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to a source/drain region. A device includes an oxide material that is positioned at least partially in a recess formed in a gate structure, wherein the oxide material contacts a conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Inventors: Xiuyu Cai, Ruilong Xie, John A. Iacoponi
  • Patent number: 8592312
    Abstract: In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition process used, thereby preventing the conductive capping layer from causing a short between the metal lines. The conductive capping layer may be deposited through electroplating, electrolessly, by atomic layer deposition (ALD), or by chemical vapor deposition (CVD), for example. In one embodiment, the present method is utilized to fabricate a semiconductor wafer. In one embodiment, the metal lines comprise copper lines, while the conductive capping layer may comprise tantalum or cobalt. The present method enables deposition of a capping layer having high electromigration resistance.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: November 26, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: E. Todd Ryan, John A. Iacoponi
  • Publication number: 20130309868
    Abstract: Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.
    Type: Application
    Filed: May 21, 2012
    Publication date: November 21, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Xiuyu Cai, Xunyuan Zhang, Ruilong Xie, Errol T. Ryan, John A. Iacoponi
  • Patent number: 8105943
    Abstract: During the patterning of sophisticated metallization systems, a damaged surface portion of a sensitive low-k dielectric material may be efficiently replaced by a well-controlled dielectric material, thereby enabling an adaptation of the material characteristics and/or the layer thickness of the replacement material. Thus, established lithography and etch techniques may be used in combination with reduced critical dimensions and dielectric materials of even further reduced permittivity.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: January 31, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Christof Streck, Volker Kahlert, John A. Iacoponi
  • Publication number: 20100025855
    Abstract: During the patterning of sophisticated metallization systems, a damaged surface portion of a sensitive low-k dielectric material may be efficiently replaced by a well-controlled dielectric material, thereby enabling an adaptation of the material characteristics and/or the layer thickness of the replacement material. Thus, established lithography and etch techniques may be used in combination with reduced critical dimensions and dielectric materials of even further reduced permittivity.
    Type: Application
    Filed: May 27, 2009
    Publication date: February 4, 2010
    Inventors: Christof Streck, Volker Kahlert, John A. Iacoponi
  • Patent number: 7557035
    Abstract: The invention provides a method of exposing low-k dielectric films to microwave radiation to cure the dielectric films. Microwave curing reduces the cure-time necessary to achieve the desired mechanical properties in the low-k films, thus decreasing the thermal exposure time for the NiSi transistor contacts. A lower thermal budget for interconnect fabrication is necessary to prevent damage to the NiSi transistor contacts and minimize thermal stressing of previously formed interconnect layers. Microwave-cured dielectric films also have higher mechanical strength and strong adhesion to overlying layers deposited during subsequent semiconductor device manufacturing steps.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: July 7, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: E. Todd Ryan, John A. Iacoponi
  • Publication number: 20090045458
    Abstract: MOS transistors for thin SOI integration and methods for fabricating such MOS transistors are provided. One exemplary method includes the steps of providing a silicon layer overlying a buried insulating layer and epitaxially growing a silicon-comprising material layer overlying the silicon layer. A trench is etched within the silicon-comprising material layer and exposing the silicon layer. An MOS transistor gate stack is formed within the trench. The MOS transistor gate stack comprises a gate insulator and a gate electrode. Ions of a conductivity-determining type are implanted within the silicon-comprising material layer using the gate stack as an implantation mask.
    Type: Application
    Filed: August 15, 2007
    Publication date: February 19, 2009
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: John A. IACOPONI, Kingsuk MAITRA
  • Publication number: 20080305617
    Abstract: In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition process used, thereby preventing the conductive capping layer from causing a short between the metal lines. The conductive capping layer may be deposited through electroplating, electrolessly, by atomic layer deposition (ALD), or by chemical vapor deposition (CVD), for example. In one embodiment, the present method is utilized to fabricate a semiconductor wafer. In one embodiment, the metal lines comprise copper lines, while the conductive capping layer may comprise tantalum or cobalt. The present method enables deposition of a capping layer having high electromigration resistance.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 11, 2008
    Inventors: E. Todd Ryan, John A. Iacoponi
  • Patent number: 6809032
    Abstract: In another aspect of the present invention, a system for detecting an endpoint in a polishing process is provided. The system comprises a polishing tool, a controllable light source, a sensor, and a controller. The polishing tool is capable of polishing a surface of a semiconductor device, wherein the semiconductor device includes a first layer comprised of a first material and a second layer comprised of a second material. The first layer is positioned above the second layer. The controllable light source is capable of delivering light having one of a plurality of a preselected frequencies to the surface of the semiconductor device. The sensor is capable of detecting the light reflected from the surface of the semiconductor device.
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: October 26, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Mauersberger, Peter J. Beckage, Paul R. Besser, Frederick N. Hause, Errol Todd Ryan, William S. Brennan, John A. Iacoponi
  • Patent number: 6649533
    Abstract: A method and an apparatus for forming an under bump metallurgy layer over a contact pad area on an interconnect formed over a semiconductor substrate are provided which eliminate a pretreatment process for removing native oxide on the contact pad area prior to the deposition of the under bump metallurgy layer. In one embodiment, the removal of a cap layer which insulates the contact pad area and the deposition of the under bump metallurgy layer are carried out without leaving a vacuum environment.
    Type: Grant
    Filed: May 5, 1999
    Date of Patent: November 18, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: John A. Iacoponi
  • Patent number: 6555479
    Abstract: A method for forming a conductive interconnect comprises forming a process layer over a structure layer and forming a mask over the process layer, the mask having an etch profile therein. An anisotropic etching process is performed to erode the mask and to form an etched region in the process layer, the etched region having a profile correlating to the etch profile. A conductive material is formed in the etched region in the process layer and any excess conductive material is removed from above an upper surface of the process layer.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: April 29, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frederick N. Hause, Paul R. Besser, Frank Mauersberger, Errol Todd Ryan, William S. Brennan, John A. Iacoponi, Peter J. Beckage
  • Patent number: 6555396
    Abstract: A method is provided to enhance endpoint detection during via etching in the processing of a semiconductor wafer. The method includes forming a first process layer and a second process layer above the first process layer. A first masking layer is formed above at least a portion of the second process layer, leaving an outer edge portion of at least the second process layer exposed. Thereafter, an etching process is used to remove the outer edge portion of the first and second layers. Once the etching is complete, the first masking layer is removed, and a second masking layer is formed above the second process layer. The second masking layer is patterned to expose portions of the first process layer, and then an etching process substantially removes the exposed portions of the first process layer to form the vias.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: April 29, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ailian Zhao, John A. Iacoponi, Thomas E. Spikes, Jr.
  • Patent number: 6514858
    Abstract: A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: February 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frederick N. Hause, Paul R. Besser, Frank Mauersberger, Errol Todd Ryan, William S. Brennan, John A. Iacoponi, Peter J. Beckage
  • Patent number: 6489240
    Abstract: A method for forming a semiconductor having improved copper interconnects is provided. The method comprises forming a first dielectric layer above a first structure layer. Thereafter, a first opening is formed in the first dielectric layer, and a first copper layer is formed above the first dielectric layer and in the first opening. A portion of the first copper layer outside of the opening is removed. A surface portion of the first copper layer is also removed from within the opening, and a second layer of copper is formed above the first layer of copper, replacing the removed surface portion.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: December 3, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John A. Iacoponi, Paul R. Besser, Frederick N. Hause, Frank Mauersberger, Errol Todd Ryan, William S. Brennan, Peter J. Beckage
  • Patent number: 6489683
    Abstract: A method is provided for forming conductive layers in semiconductor channels and vias by using ramped current densities for the electroplating process. The lower density currents are used initially to deposit a fine grain conductive layer in the vias and then higher densities are used to deposit a large grain conductive layer in the channel.
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: December 3, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey D. Lopatin, John A. Iacoponi