Abstract: Disclosed herein are various methods of forming metal-containing insulating material regions on a metal layer of a gate structure of a semiconductor device. In one example, the method includes forming a gate structure of a transistor, the gate structure comprising at least a first metal layer, and forming a first metal-containing insulating material region in the first metal layer by performing a gas cluster ion beam process using to implant gas molecules into the first metal layer.

Abstract: During the patterning of sophisticated metallization systems, a damaged surface portion of a sensitive low-k dielectric material may be efficiently replaced by a well-controlled dielectric material, thereby enabling an adaptation of the material characteristics and/or the layer thickness of the replacement material. Thus, established lithography and etch techniques may be used in combination with reduced critical dimensions and dielectric materials of even further reduced permittivity.

Abstract: Methods for producing a semiconductor device are provided. In one embodiment, a method includes the steps of: (i) fabricating a partially-completed semiconductor device including a substrate, a source/drain region in the substrate, a gate stack overlaying the substrate, and a sidewall spacer adjacent the gate stack; (ii) utilizing an anisotropic etch to remove an upper portion of the sidewall spacer while leaving intact a lower portion of the sidewall spacer overlaying the substrate; (iii) implanting ions in the source/drain region; and (iv) annealing the semiconductor device to activate the implanted ions. The step of annealing is performed with the lower portion of the sidewall spacer intact to deter the ingress of oxygen into the substrate and minimize under-oxide regrowth proximate the gate stack.

Abstract: Methods for producing a semiconductor device are provided. In one embodiment, a method includes the steps of: (i) fabricating a partially-completed semiconductor device including a substrate, a source/drain region in the substrate, a gate stack overlaying the substrate, and a sidewall spacer adjacent the gate stack; (ii) utilizing an anisotropic etch to remove an upper portion of the sidewall spacer while leaving intact a lower portion of the sidewall spacer overlaying the substrate; (iii) implanting ions in the source/drain region; and (iv) annealing the semiconductor device to activate the implanted ions. The step of annealing is performed with the lower portion of the sidewall spacer intact to deter the ingress of oxygen into the substrate and minimize under-oxide regrowth proximate the gate stack.

Abstract: During the patterning of sophisticated metallization systems, a damaged surface portion of a sensitive low-k dielectric material may be efficiently replaced by a well-controlled dielectric material, thereby enabling an adaptation of the material characteristics and/or the layer thickness of the replacement material. Thus, established lithography and etch techniques may be used in combination with reduced critical dimensions and dielectric materials of even further reduced permittivity.

Abstract: The invention provides a method of exposing low-k dielectric films to microwave radiation to cure the dielectric films. Microwave curing reduces the cure-time necessary to achieve the desired mechanical properties in the low-k films, thus decreasing the thermal exposure time for the NiSi transistor contacts. A lower thermal budget for interconnect fabrication is necessary to prevent damage to the NiSi transistor contacts and minimize thermal stressing of previously formed interconnect layers. Microwave-cured dielectric films also have higher mechanical strength and strong adhesion to overlying layers deposited during subsequent semiconductor device manufacturing steps.

Abstract: MOS transistors for thin SOI integration and methods for fabricating such MOS transistors are provided. One exemplary method includes the steps of providing a silicon layer overlying a buried insulating layer and epitaxially growing a silicon-comprising material layer overlying the silicon layer. A trench is etched within the silicon-comprising material layer and exposing the silicon layer. An MOS transistor gate stack is formed within the trench. The MOS transistor gate stack comprises a gate insulator and a gate electrode. Ions of a conductivity-determining type are implanted within the silicon-comprising material layer using the gate stack as an implantation mask.

Abstract: In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition process used, thereby preventing the conductive capping layer from causing a short between the metal lines. The conductive capping layer may be deposited through electroplating, electrolessly, by atomic layer deposition (ALD), or by chemical vapor deposition (CVD), for example. In one embodiment, the present method is utilized to fabricate a semiconductor wafer. In one embodiment, the metal lines comprise copper lines, while the conductive capping layer may comprise tantalum or cobalt. The present method enables deposition of a capping layer having high electromigration resistance.

Abstract: In another aspect of the present invention, a system for detecting an endpoint in a polishing process is provided. The system comprises a polishing tool, a controllable light source, a sensor, and a controller. The polishing tool is capable of polishing a surface of a semiconductor device, wherein the semiconductor device includes a first layer comprised of a first material and a second layer comprised of a second material. The first layer is positioned above the second layer. The controllable light source is capable of delivering light having one of a plurality of a preselected frequencies to the surface of the semiconductor device. The sensor is capable of detecting the light reflected from the surface of the semiconductor device.

Abstract: This disclosure describes use of dielectric islands embedded in metallized regions of a semiconductor device. The islands are formed in a cavity of a dielectric layer, as upright pillars attached at their base to an underlying dielectric. The islands break up the metal-dielectric interface and thus resist delamination of metal at this interface. The top of each island pillar is recessed from the cavity entrance by a selected vertical distance. This distance may be varied within certain ranges, to place the island tops in optimal positions below the top surface plane of the dielectric. Metallization introduced into the cavity containing the islands, submerges the island tops to at least a minimum distance to provide a needed minimum thickness of continuous metal. The continuous metal surface serves favorably as a last metal layer for attaching solder or for bump-bonding package to the IC; and also serves as an intermediate test or probe pad in an interior layer.

Abstract: A method and an apparatus for forming an under bump metallurgy layer over a contact pad area on an interconnect formed over a semiconductor substrate are provided which eliminate a pretreatment process for removing native oxide on the contact pad area prior to the deposition of the under bump metallurgy layer. In one embodiment, the removal of a cap layer which insulates the contact pad area and the deposition of the under bump metallurgy layer are carried out without leaving a vacuum environment.

Abstract: A method for forming a conductive interconnect comprises forming a process layer over a structure layer and forming a mask over the process layer, the mask having an etch profile therein. An anisotropic etching process is performed to erode the mask and to form an etched region in the process layer, the etched region having a profile correlating to the etch profile. A conductive material is formed in the etched region in the process layer and any excess conductive material is removed from above an upper surface of the process layer.

Abstract: A method is provided to enhance endpoint detection during via etching in the processing of a semiconductor wafer. The method includes forming a first process layer and a second process layer above the first process layer. A first masking layer is formed above at least a portion of the second process layer, leaving an outer edge portion of at least the second process layer exposed. Thereafter, an etching process is used to remove the outer edge portion of the first and second layers. Once the etching is complete, the first masking layer is removed, and a second masking layer is formed above the second process layer. The second masking layer is patterned to expose portions of the first process layer, and then an etching process substantially removes the exposed portions of the first process layer to form the vias.

Abstract: A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.

Abstract: A method for forming a semiconductor having improved copper interconnects is provided. The method comprises forming a first dielectric layer above a first structure layer. Thereafter, a first opening is formed in the first dielectric layer, and a first copper layer is formed above the first dielectric layer and in the first opening. A portion of the first copper layer outside of the opening is removed. A surface portion of the first copper layer is also removed from within the opening, and a second layer of copper is formed above the first layer of copper, replacing the removed surface portion.

Abstract: A method is provided for forming conductive layers in semiconductor channels and vias by using ramped current densities for the electroplating process. The lower density currents are used initially to deposit a fine grain conductive layer in the vias and then higher densities are used to deposit a large grain conductive layer in the channel.

Abstract: A contact formed from the backside of an integrated circuit device includes a first conductive layer on a first surface of the integrated circuit device and a second conductive layer on a second surface of the device. The two conductive layers are coupled by way of an opening through the semiconductor substrate separating the two conductive layers. A method for making the backside contact comprises forming the first conductive layer, forming an opening through the semiconductor substrate to expose at least a portion of the underside of the first conductive layer, then filling the opening with a conductive material to provide an electrical contact to the first conductive layer from the backside of the integrated circuit device.

Abstract: A method is used to test a semiconductor wafer for misaligned layers formed therein. The method comprises forming a plurality of electrically conductive connections on a surface of the semiconductor wafer. A portion of the electrically conductive connections are coupled to a voltage supply. Thereafter, a voltage contrast analysis of the surface of the semiconductor wafer is performed, and a first pattern of the plurality of electrically conductive connections coupled to the voltage supply is determined from the voltage contrast analysis. The method further comprises comparing the first pattern to a desired pattern, and indicating an error in response to the first pattern differing from the desired pattern.

Abstract: A method of forming conductive contacts or an integrated circuit device is disclosed herein. In one embodiment, the method comprises forming a transistor above a semiconducting substrate, and forming a first layer comprised of an orthosilicate glass material above the transistor and the substrate. The method further comprises forming a second layer comprised of an insulating material above the first layer, and performing at least one etching process to define an opening in the second layer for a conductive contact to be formed therein, wherein the first layer comprised of an orthosilicate glass material acts as an etch stop layer during the etching of the opening in the second layer.

Abstract: A semiconductor barrier layer and manufacturing method therefor for copper interconnects which is a tantalum-titanium, tantalum-titanium nitride, tantalum-titanium sandwich. The tantalum in the tantalum-titanium alloy bonds strongly with the semiconductor dielectric, the tantalum-titanium nitride acts as the barrier to prevent diffusion of copper, and the titanium bonds strongly with the copper.